OpenCores
URL https://opencores.org/ocsvn/wf3d/wf3d/trunk

Subversion Repositories wf3d

[/] [wf3d/] [trunk/] [implement/] [rtl/] [axi_cmn/] [fm_4k_split.v] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 specular
//=======================================================================
2
// Project Monophony
3
//   Wire-Frame 3D Graphics Accelerator IP Core
4
//
5
// File:
6
//   fm_4k_split.v
7
//
8
// Abstract:
9
//   command split module by 4KB address boundary
10
//
11
// Author:
12 9 specular
//   Kenji Ishimaru (info.info.wf3d@gmail.com)
13 5 specular
//
14
//======================================================================
15
//
16
// Copyright (c) 2015, Kenji Ishimaru
17
// All rights reserved.
18
//
19
// Redistribution and use in source and binary forms, with or without
20
// modification, are permitted provided that the following conditions are met:
21
//
22
//  -Redistributions of source code must retain the above copyright notice,
23
//   this list of conditions and the following disclaimer.
24
//  -Redistributions in binary form must reproduce the above copyright notice,
25
//   this list of conditions and the following disclaimer in the documentation
26
//   and/or other materials provided with the distribution.
27
//
28
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
30
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
32
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
33
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
34
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
35
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
36
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
37
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
38
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
//
40
// Revision History
41
 
42
 
43
`include "polyphony_def.v"
44
module fm_4k_split (
45
  clk_core,
46
  rst_x,
47
  // incoming
48
  i_brg_req,
49
  i_brg_adrs,
50
  i_brg_rw,
51
  i_brg_len,
52
  o_brg_ack,
53
  // outgoing
54
  o_brg_adrs,
55
  o_brg_len,
56
  i_brg_ack
57
);
58
`include "polyphony_axi_def.v"
59
//////////////////////////////////
60
// I/O port definition
61
//////////////////////////////////
62
  // system
63
  input clk_core;
64
  input rst_x;
65
  // incoming
66
  input          i_brg_req;
67
  input  [P_IB_ADDR_WIDTH-1:0]
68
                 i_brg_adrs;
69
  input          i_brg_rw;
70
  input  [P_IB_LEN_WIDTH-1:0]
71
                 i_brg_len;
72
  output         o_brg_ack;
73
  // outgoing
74
  output [P_IB_ADDR_WIDTH-1:0]
75
                 o_brg_adrs;
76
  output [P_IB_LEN_WIDTH-1:0]
77
                 o_brg_len;
78
  input          i_brg_ack;
79
//////////////////////////////////
80
// parameter definition
81
//////////////////////////////////
82
localparam P_IDLE = 1'b0;
83
localparam P_2ND = 1'b1;
84
//////////////////////////////////
85
// reg
86
//////////////////////////////////
87
  reg         r_state;
88
//////////////////////////////////
89
// wire
90
//////////////////////////////////
91
  wire [P_IB_ADDR_WIDTH-1:0]
92
              w_2nd_adrs;
93
  wire        w_4k_boundary;
94
  wire        w_4k_ack;
95
 
96
//////////////////////////////////
97
// assign
98
//////////////////////////////////
99
  assign w_2nd_adrs = i_brg_adrs + 1'b1;  // add 8byte address
100
  assign w_4k_boundary = (i_brg_adrs[P_IB_ADDR_WIDTH-1:(11-3)] !=
101
                          w_2nd_adrs[P_IB_ADDR_WIDTH-1:(11-3)]) & !i_brg_rw;
102
 
103
  assign w_4k_ack = (r_state == P_2ND) & i_brg_ack ;
104
  assign o_brg_adrs = (r_state == P_2ND) ? w_2nd_adrs : i_brg_adrs;
105
  assign o_brg_ack = (!i_brg_req) ? i_brg_ack :
106
                                    (w_4k_boundary) ? w_4k_ack : i_brg_ack;
107
 
108
  assign o_brg_len = (w_4k_boundary) ?  'd1 : i_brg_len;
109
//////////////////////////////////
110
// always
111
//////////////////////////////////
112
 
113
always @(posedge clk_core or negedge rst_x) begin
114
  if (~rst_x) begin
115
    r_state <= P_IDLE;
116
  end else begin
117
    case (r_state)
118
      P_IDLE: begin
119
        if (i_brg_req & i_brg_ack) begin
120
          if (w_4k_boundary) r_state <= P_2ND;
121
        end
122
      end
123
      P_2ND: begin
124
        if (i_brg_ack) begin
125
          r_state <= P_IDLE;
126
        end
127
      end
128
    endcase
129
  end
130
end
131
 
132
 
133
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.