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[/] [wf3d/] [trunk/] [implement/] [rtl/] [axi_cmn/] [fm_port_priority.v] - Blame information for rev 9

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//=======================================================================
// Project Monophony
//   Wire-Frame 3D Graphics Accelerator IP Core
//
// File:
//   fm_port_priority.v
//
// Abstract:
//   Memory Interconnect port priority decision
//
// Author:
//   Kenji Ishimaru (info.info.wf3d@gmail.com)
//
//======================================================================
//
// Copyright (c) 2016, Kenji Ishimaru
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//  -Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//  -Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
 
//`define USE_THREAD
module fm_port_priority (
  clk_core,
  rst_x,
  // port0 side Read/Write
  i_req0,
  i_we0,
  i_add0,
  i_len0,
  i_be0,
  o_cack0,
  i_strw0,
  i_dbw0,
  i_wdata_read_end0,
  o_wdata_ack0,
  o_strr0,
  o_dbr0,
  // port1 side Read/Write
  i_req1,
  i_we1,
  i_add1,
  i_len1,
  i_be1,
  o_cack1,
  i_strw1,
  i_dbw1,
  i_wdata_read_end1,
  o_wdata_ack1,
  o_strr1,
  o_dbr1,
  // port2 side Read Only
  i_req2,
  i_add2,
  i_len2,
  o_cack2,
  o_strr2,
  o_dbr2,
  // port3 side Write Only
  i_req3,
  i_add3,
  i_len3,
  i_be3,
  o_cack3,
  i_strw3,
  i_dbw3,
  i_wdata_read_end3,
  o_wdata_ack3,
  // output to bus bridge or
  // memory bus arbiter far
  o_breq,
  o_bwe,
  o_bid,
  o_badd,
  o_blen,
  i_back,
  o_bstrw,
  o_bbe,
  o_bdbw,
  i_backw,
  i_bstrr,
  i_blast,
  i_brid,
  i_bdbr
);
`include "polyphony_params.v"
////////////////////////////
// Parameter definition
////////////////////////////
parameter P_SIDLE  = 1'b0;
parameter P_SDIN   = 1'b1;
////////////////////////////
// I/O definition
////////////////////////////
// port 0
input         i_req0;         // command request
input         i_we0;          // write/read flag
input  [P_IB_ADDR_WIDTH-1:0]
              i_add0;         // address
input  [P_IB_LEN_WIDTH-1:0]
              i_len0;         // burst length
input  [P_IB_BE_WIDTH-1:0]
              i_be0;          // byte enable
output        o_cack0;        // command acknowledge
input         i_strw0;        // write data strobe
input  [P_IB_DATA_WIDTH-1:0]
              i_dbw0;         // write data
input         i_wdata_read_end0;
                              // write data end flag
output        o_wdata_ack0;   // write data acknowledge
output        o_strr0;        // read data strobe
output [P_IB_DATA_WIDTH-1:0]
              o_dbr0;         // read data
// port 1
input         i_req1;         // command request
input         i_we1;          // write/read flag
input  [P_IB_ADDR_WIDTH-1:0]
              i_add1;         // address
input  [P_IB_LEN_WIDTH-1:0]
              i_len1;         // burst length
input  [P_IB_BE_WIDTH-1:0]
              i_be1;          // byte enable
output        o_cack1;        // command acknowledge
input         i_strw1;        // write data strobe
input  [P_IB_DATA_WIDTH-1:0]
              i_dbw1;         // write data
input         i_wdata_read_end1;
                              // write data end flag
output        o_wdata_ack1;   // write data acknowledge
output        o_strr1;        // read data strobe
output  [P_IB_DATA_WIDTH-1:0]
              o_dbr1;         // read data
// port 2
input         i_req2;         // command request
input  [P_IB_ADDR_WIDTH-1:0]
              i_add2;         // address
input  [P_IB_LEN_WIDTH-1:0]
              i_len2;         // burst length
output        o_cack2;        // command acknowledge
output        o_strr2;        // read data strobe
output [P_IB_DATA_WIDTH-1:0]
              o_dbr2;         // read data
// port 3
input         i_req3;         // command request
input  [P_IB_ADDR_WIDTH-1:0]
              i_add3;         // address
input  [P_IB_LEN_WIDTH-1:0]
              i_len3;         // burst length
input  [P_IB_BE_WIDTH-1:0]
              i_be3;          // byte enable
output        o_cack3;        // command acknowledge
input         i_strw3;        // write data strobe
input  [P_IB_DATA_WIDTH-1:0]
              i_dbw3;         // write data
input         i_wdata_read_end3;
                              // write data end flag
output        o_wdata_ack3;   // write data acknowledge
// output to bus bridge or
// memory bus arbiter far
output        o_breq;         // command request
output        o_bwe;          // write/read flag
output [1:0]  o_bid;
output [P_IB_ADDR_WIDTH-1:0]
              o_badd;         // address
output [P_IB_LEN_WIDTH-1:0]
              o_blen;         // burst length
output [P_IB_BE_WIDTH-1:0]
              o_bbe;          // byte enable
input         i_back;         // command acknowledge
output        o_bstrw;        // write data strobe
output [P_IB_DATA_WIDTH-1:0]
              o_bdbw;         // write data
input         i_backw;        // write data acknowledge
input         i_bstrr;        // read data strobe
input         i_blast;
input  [1:0]  i_brid;
input  [P_IB_DATA_WIDTH-1:0]
              i_bdbr;         // read data
 
input         clk_core;        // system clock
input         rst_x;          // system reset
 
/////////////////////////
//  register definition
/////////////////////////
reg        r_breq;
reg        r_bwe;
reg [1:0]  r_bid;
reg [P_IB_ADDR_WIDTH-1:0] r_badd;
reg [P_IB_LEN_WIDTH-1:0]  r_blen;
reg [P_IB_BE_WIDTH-1:0]   r_bbe;
reg        r_back;
reg        r_bstrw;
reg [P_IB_DATA_WIDTH-1:0] r_bdbw;
reg        r_backw;
reg        r_bstrr;
reg [1:0]  r_brid;
reg [P_IB_DATA_WIDTH-1:0] r_bdbr;
// current priority
reg [1:0]  r_current_priority;  // 0 - 3
 
// read data counter
reg [P_IB_LEN_WIDTH-1:0]  r_read_cnt;
 
// write data state machine
reg        r_wstate;
// read data final out
reg        r_strr2;
reg [P_IB_DATA_WIDTH-1:0] r_dbr2;
 
/////////////////////////
//  wire definition
/////////////////////////
// current port
wire        w_req;
wire        w_we;
wire [P_IB_ADDR_WIDTH-1:0] w_add;
wire [P_IB_LEN_WIDTH-1:0]  w_len;
wire [P_IB_BE_WIDTH-1:0]   w_be;
wire        w_strw;
wire [P_IB_DATA_WIDTH-1:0] w_dbw;
wire        w_wdata_read_end;
wire        w_wdata_read;
wire        w_write_burst;
wire        w_wdata_idle;
wire        w_rfifo_ok;
 
// masked back
wire      w_back;
 
// bridge port
wire      w_breq;
wire      w_bstrw;
 
wire [3:0] w_sreq;
wire [1:0] w_decide_port;
wire       w_wstate_idle;
wire       w_wstate_din;
// fifo port
wire       w_fifo_full;
wire [2+P_IB_LEN_WIDTH-1:0]
           w_fifo_din;
wire [2+P_IB_LEN_WIDTH-1:0]
           w_fifo_dout;
wire       w_fifo_write;
wire [P_IB_LEN_WIDTH-1:0]
           w_current_read_len;
wire [1:0] w_current_read_pr;
wire       w_read_end;
wire       w_set_priority;
wire [1:0] w_wdata_port;
 
// read data final out
wire        w_strr2;
wire [P_IB_DATA_WIDTH-1:0] w_dbr2;
 
/////////////////////////
//  assign statement
/////////////////////////
// masked back
assign w_back = r_back;
 
assign w_sreq = {i_req3,i_req2,i_req1,i_req0};
assign w_decide_port = f_decide_port(w_sreq,r_current_priority);
assign w_wstate_idle = (r_wstate == P_SIDLE);
assign w_wstate_din = (r_wstate == P_SDIN);
assign w_wdata_idle = (w_we) ?  r_backw & w_wstate_idle :  w_wstate_idle;
assign w_wdata_port = (w_wstate_idle) ? w_decide_port : r_current_priority;
assign w_wdata_read = w_wstate_din | (w_req & w_we & w_back);
`ifdef USE_THREAD
assign w_rfifo_ok = 1'b1;
`else
assign w_rfifo_ok = (!w_we) ?  !w_fifo_full :  1'b1;
`endif
// command end cycle flag
assign w_set_priority = w_req & w_back & w_wdata_idle;
 
// port0
assign o_cack0 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd0);
assign o_wdata_ack0 = r_backw & w_wdata_read & (w_wdata_port == 2'd0);
`ifdef USE_THREAD
assign o_strr0 = r_bstrr & (r_brid == 2'd0);
`else
assign o_strr0 = r_bstrr & (w_current_read_pr == 2'd0);
`endif
assign o_dbr0 = r_bdbr;
 
// port1
assign o_cack1 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd1);
assign o_wdata_ack1 = r_backw & w_wdata_read & (w_wdata_port == 2'd1);
`ifdef USE_THREAD
assign o_strr1 = r_bstrr & (r_brid == 2'd1);
`else
assign o_strr1 = r_bstrr & (w_current_read_pr == 2'd1);
`endif
assign o_dbr1 = r_bdbr;
 
// port2
assign o_cack2 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd2);
`ifdef USE_THREAD
assign w_strr2 = r_bstrr & (r_brid == 2'd2);
`else
assign w_strr2 = r_bstrr & (w_current_read_pr == 2'd2);
`endif
assign w_dbr2 = r_bdbr;
assign o_strr2 = r_strr2;
assign o_dbr2 = r_dbr2;
 
// port3
assign o_cack3 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd3);
assign o_wdata_ack3 = r_backw & w_wdata_read & (w_wdata_port == 2'd3);
 
// current port
assign w_req = (w_decide_port == 2'd0) ? i_req0 :
               (w_decide_port == 2'd1) ? i_req1 :
               (w_decide_port == 2'd2) ? i_req2 : i_req3;
assign w_we  = (w_decide_port == 2'd0) ? i_we0 :
               (w_decide_port == 2'd1) ? i_we1 :
               (w_decide_port == 2'd2) ? 1'b0 : 1'b1;
assign w_add = (w_decide_port == 2'd0) ? i_add0 :
               (w_decide_port == 2'd1) ? i_add1 :
               (w_decide_port == 2'd2) ? i_add2 :i_add3;
assign w_len = (w_decide_port == 2'd0) ? i_len0 :
               (w_decide_port == 2'd1) ? i_len1 :
               (w_decide_port == 2'd2) ? i_len2 : i_len3;
assign w_be  = (w_wdata_port == 2'd0) ? i_be0 :
               (w_wdata_port == 2'd1) ? i_be1 :
               (w_wdata_port == 2'd2) ? 8'h00 : i_be3;
assign w_dbw = (w_wdata_port == 2'd0) ? i_dbw0 :
               (w_wdata_port == 2'd1) ? i_dbw1 :
               (w_wdata_port == 2'd2) ?  32'h0000_0000 : i_dbw3;
assign w_strw = (w_wdata_port == 2'd0) ? i_strw0 :
                (w_wdata_port == 2'd1) ? i_strw1 :
                (w_wdata_port == 2'd2) ? 1'b0 : i_strw3;
assign w_wdata_read_end = (w_wdata_port == 2'd0) ? (i_wdata_read_end0 & r_backw) :
                          (w_wdata_port == 2'd1) ? (i_wdata_read_end1 & r_backw) :
                          (w_wdata_port == 2'd3) ? (i_wdata_read_end3 & r_backw) : 1'b0;
 
assign w_write_burst = w_req & w_we & (w_len != 1) & w_back & r_backw;
 
 
// bridge port
//assign w_breq = w_req & w_back & w_wdata_idle;
// 2004/11/27
  assign w_breq = w_req & w_back & w_wdata_idle & w_rfifo_ok;
 
assign w_bstrw =  w_strw & w_wdata_read & r_backw;
// bridge port output connection
assign o_breq = r_breq;
assign o_bwe = r_bwe;
assign o_bid = r_bid;
assign o_badd = r_badd;
assign o_blen = r_blen;
assign o_bstrw = r_bstrw;
assign o_bbe = r_bbe;
assign o_bdbw = r_bdbw;
 
// fifo port
assign w_fifo_din = {w_decide_port,w_len};
assign w_fifo_write = w_req & w_back & !w_we & w_set_priority;
assign {w_current_read_pr,w_current_read_len} = w_fifo_dout;
assign w_read_end = (r_read_cnt == w_current_read_len) & r_bstrr;
 
// debug
wire w_wrong_id;
assign w_wrong_id = r_bstrr & (w_current_read_pr != r_brid);
 
/////////////////////////
//  function statement
/////////////////////////
function [1:0] f_decide_port;
  input [3:0] req;
  input [1:0] cp;
  begin
    case (req)
      4'b0000: begin
        // no request
        f_decide_port = cp;
      end
      4'b0001: begin
        // only port0 request
        f_decide_port = 2'd0;
      end
      4'b0010: begin
        // only port1 request
        f_decide_port = 2'b1;
      end
      4'b0011: begin
        // simultaneous request port 1 & 0
        case (cp)
          2'b00 : f_decide_port = 2'd1;
          default : f_decide_port = 2'd0;
        endcase
      end
      4'b0100: begin
        // only port2 request
        f_decide_port = 2'd2;
      end
      4'b0101: begin
        // simultaneous request port 2 & 0
        case (cp)
          2'b00,
          2'b01 : f_decide_port = 2'd2;
          default : f_decide_port = 2'd0;
        endcase
      end
      4'b0110: begin
        // simultaneous request port 2 & 1
        case (cp)
          2'b01 : f_decide_port = 2'd2;
          default : f_decide_port = 2'd1;
        endcase
      end
      4'b0111: begin
        // simultaneous request port 2 & 1 & 0
        case (cp)
          2'b00 : f_decide_port = 2'd1;
          2'b01 : f_decide_port = 2'd2;
          default : f_decide_port = 2'd0;
        endcase
      end
      4'b1000: begin
        // port 3 request
        f_decide_port = 2'd3;
      end
      4'b1001: begin
        // only port3&0 request
        case (cp)
          2'd0,
          2'd1,
          2'd2 : f_decide_port = 2'd3;
          default : f_decide_port = 2'd0;
        endcase
      end
      4'b1010: begin
        // only port 3 & 1 request
        case (cp)
          2'd1,
          2'd2 : f_decide_port = 2'd3;
          default : f_decide_port = 2'd1;
        endcase
      end
      4'b1011: begin
        // simultaneous request port 3 & 1 & 0
        case (cp)
          2'd0 : f_decide_port = 2'd1;
          2'd1,
          2'd2 : f_decide_port = 2'd3;
          default : f_decide_port = 2'd0;
        endcase
      end
      4'b1100: begin
        // simultaneous request port 3 & 2
        case (cp)
          2'd2 : f_decide_port = 2'd3;
          default : f_decide_port = 2'd2;
        endcase
      end
      4'b1101: begin
        // simultaneous request port 3 & 2 & 0
        case (cp)
          2'd0,
          2'd1 : f_decide_port = 2'd2;
          2'd2 : f_decide_port = 2'd3;
          default : f_decide_port = 2'd0;
        endcase
      end
      4'b1110: begin
        // simultaneous request port 3 & 2 & 1
        case (cp)
          2'd1 : f_decide_port = 2'd2;
          2'd2 : f_decide_port = 2'd3;
          default : f_decide_port = 2'd1;
        endcase
      end
      4'b1111: begin
        // simultaneous request port 3 & 2 & 1 & 0
        case (cp)
          2'd0 : f_decide_port = 2'd1;
          2'd1 : f_decide_port = 2'd2;
          2'd2 : f_decide_port = 2'd3;
          2'd3 : f_decide_port = 2'd0;
          default : f_decide_port = 2'd0;
        endcase
      end
      default : f_decide_port = 2'd0;
    endcase
    // test : port2 always has top priority
    if (req[2]) f_decide_port = 2'd2;
  end
endfunction
 
/////////////////////////
//  always statement
/////////////////////////
// write data state machine
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_wstate <= P_SIDLE;
  end else begin
    case (r_wstate)
      P_SIDLE :  // Idle
        begin
          if (w_write_burst) begin
            r_wstate <= P_SDIN;
          end
        end
      P_SDIN :   // Getting write data & be
        begin
          if (w_wdata_read_end) begin
            r_wstate <= P_SIDLE;
          end
        end
      default : r_wstate <= r_wstate;
    endcase
  end
end
 
 
// current priority
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_current_priority <= 2'd3;   // lowest priority port number
  end else begin
    if (w_set_priority) begin
      r_current_priority <= w_decide_port;
    end
  end
end
// read data counter
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_read_cnt <= 1;
  end else begin
    if (w_read_end) begin
      r_read_cnt <= 1;
    end else if (r_bstrr) begin
      r_read_cnt <= r_read_cnt + 1'b1;
    end
  end
end
 
// bus bridge (or memory arbiter far) port
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_breq <= 1'b0;
  end else begin
    r_breq <= w_breq;
  end
end
 
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_bstrw <= 1'b0;
  end else begin
    r_bstrw <= w_bstrw;
  end
end
 
always @(posedge clk_core) begin
`ifdef USE_THREAD
  r_bid <= (w_decide_port == 2'd0) ? 2'd0 :
           (w_decide_port == 2'd1) ? 2'd1 :
           (w_decide_port == 2'd2) ? 2'd2 : 2'd3;
`else
  r_bid <= 2'd0;
`endif
  r_bwe <= w_we;
  r_badd <= w_add;
  r_blen <= w_len;
  r_bbe <= w_be;
  r_bdbw <= w_dbw;
end
 
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_bstrr <= 1'b0;
  end else begin
    r_bstrr <= i_bstrr;
  end
end
 
always @(posedge clk_core) begin
  r_brid <= i_brid;
  r_bdbr <= i_bdbr;
end
 
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_back <= 1'b0;
    r_backw <= 1'b0;
  end else begin
    r_back <= i_back;
    r_backw <= i_backw;
  end
end
 
// read data strobe & outout (Read Only Port)
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_strr2 <= 1'b0;
  end else begin
    r_strr2 <= w_strr2;
  end
end
 
always @(posedge clk_core) begin
  r_dbr2 <= w_dbr2;
end
 
/////////////////////////
//  module instantiation
/////////////////////////
// read data priority fifo
// contain port number + burst length
wire [7:0] w_dnum;
wire       w_empty;
`ifdef USE_THREAD
`else
fm_cmn_bfifo #(2+P_IB_LEN_WIDTH,7) fifo (
  .clk_core(clk_core),
  .rst_x(rst_x),
  .i_wstrobe(w_fifo_write),
  .i_dt(w_fifo_din),
  .o_full(w_fifo_full),
  .i_renable(w_read_end),
  .o_dt(w_fifo_dout),
  .o_empty(w_empty),
  .o_dnum(w_dnum)
);
`endif
 
 
wire    w_error;
assign w_error = w_empty & r_bstrr;
 
reg [15:0]    r_req_cnt;
reg [15:0]    r_acc_cnt;
 
always @(posedge clk_core or negedge rst_x) begin
  if (~rst_x) begin
    r_req_cnt <= 'd0;
    r_acc_cnt <= 'd0;
  end else begin
    if (w_fifo_write) r_req_cnt <= r_req_cnt + w_len;
   if (i_bstrr) r_acc_cnt <= r_acc_cnt + 1'b1;
 
  end
end
endmodule

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[/] [wf3d/] [trunk/] [implement/] [rtl/] [axi_cmn/] [fm_port_priority.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	5	specular	`//=======================================================================`
2			`// Project Monophony`
3			`// Wire-Frame 3D Graphics Accelerator IP Core`
4			`//`
5			`// File:`
6			`// fm_port_priority.v`
7			`//`
8			`// Abstract:`
9			`// Memory Interconnect port priority decision`
10			`//`
11			`// Author:`
12	9	specular	`// Kenji Ishimaru (info.info.wf3d@gmail.com)`
13	5	specular	`//`
14			`//======================================================================`
15			`//`
16			`// Copyright (c) 2016, Kenji Ishimaru`
17			`// All rights reserved.`
18			`//`
19			`// Redistribution and use in source and binary forms, with or without`
20			`// modification, are permitted provided that the following conditions are met:`
21			`//`
22			`// -Redistributions of source code must retain the above copyright notice,`
23			`// this list of conditions and the following disclaimer.`
24			`// -Redistributions in binary form must reproduce the above copyright notice,`
25			`// this list of conditions and the following disclaimer in the documentation`
26			`// and/or other materials provided with the distribution.`
27			`//`
28			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
29			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
30			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
31			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR`
32			`// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,`
33			`// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,`
38			`// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`//`
40			`// Revision History`
41
42			//`define USE_THREAD
43			`module fm_port_priority (`
44			`clk_core,`
45			`rst_x,`
46			`// port0 side Read/Write`
47			`i_req0,`
48			`i_we0,`
49			`i_add0,`
50			`i_len0,`
51			`i_be0,`
52			`o_cack0,`
53			`i_strw0,`
54			`i_dbw0,`
55			`i_wdata_read_end0,`
56			`o_wdata_ack0,`
57			`o_strr0,`
58			`o_dbr0,`
59			`// port1 side Read/Write`
60			`i_req1,`
61			`i_we1,`
62			`i_add1,`
63			`i_len1,`
64			`i_be1,`
65			`o_cack1,`
66			`i_strw1,`
67			`i_dbw1,`
68			`i_wdata_read_end1,`
69			`o_wdata_ack1,`
70			`o_strr1,`
71			`o_dbr1,`
72			`// port2 side Read Only`
73			`i_req2,`
74			`i_add2,`
75			`i_len2,`
76			`o_cack2,`
77			`o_strr2,`
78			`o_dbr2,`
79			`// port3 side Write Only`
80			`i_req3,`
81			`i_add3,`
82			`i_len3,`
83			`i_be3,`
84			`o_cack3,`
85			`i_strw3,`
86			`i_dbw3,`
87			`i_wdata_read_end3,`
88			`o_wdata_ack3,`
89			`// output to bus bridge or`
90			`// memory bus arbiter far`
91			`o_breq,`
92			`o_bwe,`
93			`o_bid,`
94			`o_badd,`
95			`o_blen,`
96			`i_back,`
97			`o_bstrw,`
98			`o_bbe,`
99			`o_bdbw,`
100			`i_backw,`
101			`i_bstrr,`
102			`i_blast,`
103			`i_brid,`
104			`i_bdbr`
105			`);`
106			`include "polyphony_params.v"
107			`////////////////////////////`
108			`// Parameter definition`
109			`////////////////////////////`
110			`parameter P_SIDLE = 1'b0;`
111			`parameter P_SDIN = 1'b1;`
112			`////////////////////////////`
113			`// I/O definition`
114			`////////////////////////////`
115			`// port 0`
116			`input i_req0; // command request`
117			`input i_we0; // write/read flag`
118			`input [P_IB_ADDR_WIDTH-1:0]`
119			`i_add0; // address`
120			`input [P_IB_LEN_WIDTH-1:0]`
121			`i_len0; // burst length`
122			`input [P_IB_BE_WIDTH-1:0]`
123			`i_be0; // byte enable`
124			`output o_cack0; // command acknowledge`
125			`input i_strw0; // write data strobe`
126			`input [P_IB_DATA_WIDTH-1:0]`
127			`i_dbw0; // write data`
128			`input i_wdata_read_end0;`
129			`// write data end flag`
130			`output o_wdata_ack0; // write data acknowledge`
131			`output o_strr0; // read data strobe`
132			`output [P_IB_DATA_WIDTH-1:0]`
133			`o_dbr0; // read data`
134			`// port 1`
135			`input i_req1; // command request`
136			`input i_we1; // write/read flag`
137			`input [P_IB_ADDR_WIDTH-1:0]`
138			`i_add1; // address`
139			`input [P_IB_LEN_WIDTH-1:0]`
140			`i_len1; // burst length`
141			`input [P_IB_BE_WIDTH-1:0]`
142			`i_be1; // byte enable`
143			`output o_cack1; // command acknowledge`
144			`input i_strw1; // write data strobe`
145			`input [P_IB_DATA_WIDTH-1:0]`
146			`i_dbw1; // write data`
147			`input i_wdata_read_end1;`
148			`// write data end flag`
149			`output o_wdata_ack1; // write data acknowledge`
150			`output o_strr1; // read data strobe`
151			`output [P_IB_DATA_WIDTH-1:0]`
152			`o_dbr1; // read data`
153			`// port 2`
154			`input i_req2; // command request`
155			`input [P_IB_ADDR_WIDTH-1:0]`
156			`i_add2; // address`
157			`input [P_IB_LEN_WIDTH-1:0]`
158			`i_len2; // burst length`
159			`output o_cack2; // command acknowledge`
160			`output o_strr2; // read data strobe`
161			`output [P_IB_DATA_WIDTH-1:0]`
162			`o_dbr2; // read data`
163			`// port 3`
164			`input i_req3; // command request`
165			`input [P_IB_ADDR_WIDTH-1:0]`
166			`i_add3; // address`
167			`input [P_IB_LEN_WIDTH-1:0]`
168			`i_len3; // burst length`
169			`input [P_IB_BE_WIDTH-1:0]`
170			`i_be3; // byte enable`
171			`output o_cack3; // command acknowledge`
172			`input i_strw3; // write data strobe`
173			`input [P_IB_DATA_WIDTH-1:0]`
174			`i_dbw3; // write data`
175			`input i_wdata_read_end3;`
176			`// write data end flag`
177			`output o_wdata_ack3; // write data acknowledge`
178			`// output to bus bridge or`
179			`// memory bus arbiter far`
180			`output o_breq; // command request`
181			`output o_bwe; // write/read flag`
182			`output [1:0] o_bid;`
183			`output [P_IB_ADDR_WIDTH-1:0]`
184			`o_badd; // address`
185			`output [P_IB_LEN_WIDTH-1:0]`
186			`o_blen; // burst length`
187			`output [P_IB_BE_WIDTH-1:0]`
188			`o_bbe; // byte enable`
189			`input i_back; // command acknowledge`
190			`output o_bstrw; // write data strobe`
191			`output [P_IB_DATA_WIDTH-1:0]`
192			`o_bdbw; // write data`
193			`input i_backw; // write data acknowledge`
194			`input i_bstrr; // read data strobe`
195			`input i_blast;`
196			`input [1:0] i_brid;`
197			`input [P_IB_DATA_WIDTH-1:0]`
198			`i_bdbr; // read data`
199
200			`input clk_core; // system clock`
201			`input rst_x; // system reset`
202
203			`/////////////////////////`
204			`// register definition`
205			`/////////////////////////`
206			`reg r_breq;`
207			`reg r_bwe;`
208			`reg [1:0] r_bid;`
209			`reg [P_IB_ADDR_WIDTH-1:0] r_badd;`
210			`reg [P_IB_LEN_WIDTH-1:0] r_blen;`
211			`reg [P_IB_BE_WIDTH-1:0] r_bbe;`
212			`reg r_back;`
213			`reg r_bstrw;`
214			`reg [P_IB_DATA_WIDTH-1:0] r_bdbw;`
215			`reg r_backw;`
216			`reg r_bstrr;`
217			`reg [1:0] r_brid;`
218			`reg [P_IB_DATA_WIDTH-1:0] r_bdbr;`
219			`// current priority`
220			`reg [1:0] r_current_priority; // 0 - 3`
221
222			`// read data counter`
223			`reg [P_IB_LEN_WIDTH-1:0] r_read_cnt;`
224
225			`// write data state machine`
226			`reg r_wstate;`
227			`// read data final out`
228			`reg r_strr2;`
229			`reg [P_IB_DATA_WIDTH-1:0] r_dbr2;`
230
231			`/////////////////////////`
232			`// wire definition`
233			`/////////////////////////`
234			`// current port`
235			`wire w_req;`
236			`wire w_we;`
237			`wire [P_IB_ADDR_WIDTH-1:0] w_add;`
238			`wire [P_IB_LEN_WIDTH-1:0] w_len;`
239			`wire [P_IB_BE_WIDTH-1:0] w_be;`
240			`wire w_strw;`
241			`wire [P_IB_DATA_WIDTH-1:0] w_dbw;`
242			`wire w_wdata_read_end;`
243			`wire w_wdata_read;`
244			`wire w_write_burst;`
245			`wire w_wdata_idle;`
246			`wire w_rfifo_ok;`
247
248			`// masked back`
249			`wire w_back;`
250
251			`// bridge port`
252			`wire w_breq;`
253			`wire w_bstrw;`
254
255			`wire [3:0] w_sreq;`
256			`wire [1:0] w_decide_port;`
257			`wire w_wstate_idle;`
258			`wire w_wstate_din;`
259			`// fifo port`
260			`wire w_fifo_full;`
261			`wire [2+P_IB_LEN_WIDTH-1:0]`
262			`w_fifo_din;`
263			`wire [2+P_IB_LEN_WIDTH-1:0]`
264			`w_fifo_dout;`
265			`wire w_fifo_write;`
266			`wire [P_IB_LEN_WIDTH-1:0]`
267			`w_current_read_len;`
268			`wire [1:0] w_current_read_pr;`
269			`wire w_read_end;`
270			`wire w_set_priority;`
271			`wire [1:0] w_wdata_port;`
272
273			`// read data final out`
274			`wire w_strr2;`
275			`wire [P_IB_DATA_WIDTH-1:0] w_dbr2;`
276
277			`/////////////////////////`
278			`// assign statement`
279			`/////////////////////////`
280			`// masked back`
281			`assign w_back = r_back;`
282
283			`assign w_sreq = {i_req3,i_req2,i_req1,i_req0};`
284			`assign w_decide_port = f_decide_port(w_sreq,r_current_priority);`
285			`assign w_wstate_idle = (r_wstate == P_SIDLE);`
286			`assign w_wstate_din = (r_wstate == P_SDIN);`
287			`assign w_wdata_idle = (w_we) ? r_backw & w_wstate_idle : w_wstate_idle;`
288			`assign w_wdata_port = (w_wstate_idle) ? w_decide_port : r_current_priority;`
289			`assign w_wdata_read = w_wstate_din \| (w_req & w_we & w_back);`
290			`ifdef USE_THREAD
291			`assign w_rfifo_ok = 1'b1;`
292			`else
293			`assign w_rfifo_ok = (!w_we) ? !w_fifo_full : 1'b1;`
294			`endif
295			`// command end cycle flag`
296			`assign w_set_priority = w_req & w_back & w_wdata_idle;`
297
298			`// port0`
299			`assign o_cack0 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd0);`
300			`assign o_wdata_ack0 = r_backw & w_wdata_read & (w_wdata_port == 2'd0);`
301			`ifdef USE_THREAD
302			`assign o_strr0 = r_bstrr & (r_brid == 2'd0);`
303			`else
304			`assign o_strr0 = r_bstrr & (w_current_read_pr == 2'd0);`
305			`endif
306			`assign o_dbr0 = r_bdbr;`
307
308			`// port1`
309			`assign o_cack1 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd1);`
310			`assign o_wdata_ack1 = r_backw & w_wdata_read & (w_wdata_port == 2'd1);`
311			`ifdef USE_THREAD
312			`assign o_strr1 = r_bstrr & (r_brid == 2'd1);`
313			`else
314			`assign o_strr1 = r_bstrr & (w_current_read_pr == 2'd1);`
315			`endif
316			`assign o_dbr1 = r_bdbr;`
317
318			`// port2`
319			`assign o_cack2 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd2);`
320			`ifdef USE_THREAD
321			`assign w_strr2 = r_bstrr & (r_brid == 2'd2);`
322			`else
323			`assign w_strr2 = r_bstrr & (w_current_read_pr == 2'd2);`
324			`endif
325			`assign w_dbr2 = r_bdbr;`
326			`assign o_strr2 = r_strr2;`
327			`assign o_dbr2 = r_dbr2;`
328
329			`// port3`
330			`assign o_cack3 = w_set_priority & w_rfifo_ok & (w_decide_port == 2'd3);`
331			`assign o_wdata_ack3 = r_backw & w_wdata_read & (w_wdata_port == 2'd3);`
332
333			`// current port`
334			`assign w_req = (w_decide_port == 2'd0) ? i_req0 :`
335			`(w_decide_port == 2'd1) ? i_req1 :`
336			`(w_decide_port == 2'd2) ? i_req2 : i_req3;`
337			`assign w_we = (w_decide_port == 2'd0) ? i_we0 :`
338			`(w_decide_port == 2'd1) ? i_we1 :`
339			`(w_decide_port == 2'd2) ? 1'b0 : 1'b1;`
340			`assign w_add = (w_decide_port == 2'd0) ? i_add0 :`
341			`(w_decide_port == 2'd1) ? i_add1 :`
342			`(w_decide_port == 2'd2) ? i_add2 :i_add3;`
343			`assign w_len = (w_decide_port == 2'd0) ? i_len0 :`
344			`(w_decide_port == 2'd1) ? i_len1 :`
345			`(w_decide_port == 2'd2) ? i_len2 : i_len3;`
346			`assign w_be = (w_wdata_port == 2'd0) ? i_be0 :`
347			`(w_wdata_port == 2'd1) ? i_be1 :`
348			`(w_wdata_port == 2'd2) ? 8'h00 : i_be3;`
349			`assign w_dbw = (w_wdata_port == 2'd0) ? i_dbw0 :`
350			`(w_wdata_port == 2'd1) ? i_dbw1 :`
351			`(w_wdata_port == 2'd2) ? 32'h0000_0000 : i_dbw3;`
352			`assign w_strw = (w_wdata_port == 2'd0) ? i_strw0 :`
353			`(w_wdata_port == 2'd1) ? i_strw1 :`
354			`(w_wdata_port == 2'd2) ? 1'b0 : i_strw3;`
355			`assign w_wdata_read_end = (w_wdata_port == 2'd0) ? (i_wdata_read_end0 & r_backw) :`
356			`(w_wdata_port == 2'd1) ? (i_wdata_read_end1 & r_backw) :`
357			`(w_wdata_port == 2'd3) ? (i_wdata_read_end3 & r_backw) : 1'b0;`
358
359			`assign w_write_burst = w_req & w_we & (w_len != 1) & w_back & r_backw;`
360
361
362			`// bridge port`
363			`//assign w_breq = w_req & w_back & w_wdata_idle;`
364			`// 2004/11/27`
365			`assign w_breq = w_req & w_back & w_wdata_idle & w_rfifo_ok;`
366
367			`assign w_bstrw = w_strw & w_wdata_read & r_backw;`
368			`// bridge port output connection`
369			`assign o_breq = r_breq;`
370			`assign o_bwe = r_bwe;`
371			`assign o_bid = r_bid;`
372			`assign o_badd = r_badd;`
373			`assign o_blen = r_blen;`
374			`assign o_bstrw = r_bstrw;`
375			`assign o_bbe = r_bbe;`
376			`assign o_bdbw = r_bdbw;`
377
378			`// fifo port`
379			`assign w_fifo_din = {w_decide_port,w_len};`
380			`assign w_fifo_write = w_req & w_back & !w_we & w_set_priority;`
381			`assign {w_current_read_pr,w_current_read_len} = w_fifo_dout;`
382			`assign w_read_end = (r_read_cnt == w_current_read_len) & r_bstrr;`
383
384			`// debug`
385			`wire w_wrong_id;`
386			`assign w_wrong_id = r_bstrr & (w_current_read_pr != r_brid);`
387
388			`/////////////////////////`
389			`// function statement`
390			`/////////////////////////`
391			`function [1:0] f_decide_port;`
392			`input [3:0] req;`
393			`input [1:0] cp;`
394			`begin`
395			`case (req)`
396			`4'b0000: begin`
397			`// no request`
398			`f_decide_port = cp;`
399			`end`
400			`4'b0001: begin`
401			`// only port0 request`
402			`f_decide_port = 2'd0;`
403			`end`
404			`4'b0010: begin`
405			`// only port1 request`
406			`f_decide_port = 2'b1;`
407			`end`
408			`4'b0011: begin`
409			`// simultaneous request port 1 & 0`
410			`case (cp)`
411			`2'b00 : f_decide_port = 2'd1;`
412			`default : f_decide_port = 2'd0;`
413			`endcase`
414			`end`
415			`4'b0100: begin`
416			`// only port2 request`
417			`f_decide_port = 2'd2;`
418			`end`
419			`4'b0101: begin`
420			`// simultaneous request port 2 & 0`
421			`case (cp)`
422			`2'b00,`
423			`2'b01 : f_decide_port = 2'd2;`
424			`default : f_decide_port = 2'd0;`
425			`endcase`
426			`end`
427			`4'b0110: begin`
428			`// simultaneous request port 2 & 1`
429			`case (cp)`
430			`2'b01 : f_decide_port = 2'd2;`
431			`default : f_decide_port = 2'd1;`
432			`endcase`
433			`end`
434			`4'b0111: begin`
435			`// simultaneous request port 2 & 1 & 0`
436			`case (cp)`
437			`2'b00 : f_decide_port = 2'd1;`
438			`2'b01 : f_decide_port = 2'd2;`
439			`default : f_decide_port = 2'd0;`
440			`endcase`
441			`end`
442			`4'b1000: begin`
443			`// port 3 request`
444			`f_decide_port = 2'd3;`
445			`end`
446			`4'b1001: begin`
447			`// only port3&0 request`
448			`case (cp)`
449			`2'd0,`
450			`2'd1,`
451			`2'd2 : f_decide_port = 2'd3;`
452			`default : f_decide_port = 2'd0;`
453			`endcase`
454			`end`
455			`4'b1010: begin`
456			`// only port 3 & 1 request`
457			`case (cp)`
458			`2'd1,`
459			`2'd2 : f_decide_port = 2'd3;`
460			`default : f_decide_port = 2'd1;`
461			`endcase`
462			`end`
463			`4'b1011: begin`
464			`// simultaneous request port 3 & 1 & 0`
465			`case (cp)`
466			`2'd0 : f_decide_port = 2'd1;`
467			`2'd1,`
468			`2'd2 : f_decide_port = 2'd3;`
469			`default : f_decide_port = 2'd0;`
470			`endcase`
471			`end`
472			`4'b1100: begin`
473			`// simultaneous request port 3 & 2`
474			`case (cp)`
475			`2'd2 : f_decide_port = 2'd3;`
476			`default : f_decide_port = 2'd2;`
477			`endcase`
478			`end`
479			`4'b1101: begin`
480			`// simultaneous request port 3 & 2 & 0`
481			`case (cp)`
482			`2'd0,`
483			`2'd1 : f_decide_port = 2'd2;`
484			`2'd2 : f_decide_port = 2'd3;`
485			`default : f_decide_port = 2'd0;`
486			`endcase`
487			`end`
488			`4'b1110: begin`
489			`// simultaneous request port 3 & 2 & 1`
490			`case (cp)`
491			`2'd1 : f_decide_port = 2'd2;`
492			`2'd2 : f_decide_port = 2'd3;`
493			`default : f_decide_port = 2'd1;`
494			`endcase`
495			`end`
496			`4'b1111: begin`
497			`// simultaneous request port 3 & 2 & 1 & 0`
498			`case (cp)`
499			`2'd0 : f_decide_port = 2'd1;`
500			`2'd1 : f_decide_port = 2'd2;`
501			`2'd2 : f_decide_port = 2'd3;`
502			`2'd3 : f_decide_port = 2'd0;`
503			`default : f_decide_port = 2'd0;`
504			`endcase`
505			`end`
506			`default : f_decide_port = 2'd0;`
507			`endcase`
508			`// test : port2 always has top priority`
509			`if (req[2]) f_decide_port = 2'd2;`
510			`end`
511			`endfunction`
512
513			`/////////////////////////`
514			`// always statement`
515			`/////////////////////////`
516			`// write data state machine`
517			`always @(posedge clk_core or negedge rst_x) begin`
518			`if (~rst_x) begin`
519			`r_wstate <= P_SIDLE;`
520			`end else begin`
521			`case (r_wstate)`
522			`P_SIDLE : // Idle`
523			`begin`
524			`if (w_write_burst) begin`
525			`r_wstate <= P_SDIN;`
526			`end`
527			`end`
528			`P_SDIN : // Getting write data & be`
529			`begin`
530			`if (w_wdata_read_end) begin`
531			`r_wstate <= P_SIDLE;`
532			`end`
533			`end`
534			`default : r_wstate <= r_wstate;`
535			`endcase`
536			`end`
537			`end`
538
539
540			`// current priority`
541			`always @(posedge clk_core or negedge rst_x) begin`
542			`if (~rst_x) begin`
543			`r_current_priority <= 2'd3; // lowest priority port number`
544			`end else begin`
545			`if (w_set_priority) begin`
546			`r_current_priority <= w_decide_port;`
547			`end`
548			`end`
549			`end`
550			`// read data counter`
551			`always @(posedge clk_core or negedge rst_x) begin`
552			`if (~rst_x) begin`
553			`r_read_cnt <= 1;`
554			`end else begin`
555			`if (w_read_end) begin`
556			`r_read_cnt <= 1;`
557			`end else if (r_bstrr) begin`
558			`r_read_cnt <= r_read_cnt + 1'b1;`
559			`end`
560			`end`
561			`end`
562
563			`// bus bridge (or memory arbiter far) port`
564			`always @(posedge clk_core or negedge rst_x) begin`
565			`if (~rst_x) begin`
566			`r_breq <= 1'b0;`
567			`end else begin`
568			`r_breq <= w_breq;`
569			`end`
570			`end`
571
572			`always @(posedge clk_core or negedge rst_x) begin`
573			`if (~rst_x) begin`
574			`r_bstrw <= 1'b0;`
575			`end else begin`
576			`r_bstrw <= w_bstrw;`
577			`end`
578			`end`
579
580			`always @(posedge clk_core) begin`
581			`ifdef USE_THREAD
582			`r_bid <= (w_decide_port == 2'd0) ? 2'd0 :`
583			`(w_decide_port == 2'd1) ? 2'd1 :`
584			`(w_decide_port == 2'd2) ? 2'd2 : 2'd3;`
585			`else
586			`r_bid <= 2'd0;`
587			`endif
588			`r_bwe <= w_we;`
589			`r_badd <= w_add;`
590			`r_blen <= w_len;`
591			`r_bbe <= w_be;`
592			`r_bdbw <= w_dbw;`
593			`end`
594
595			`always @(posedge clk_core or negedge rst_x) begin`
596			`if (~rst_x) begin`
597			`r_bstrr <= 1'b0;`
598			`end else begin`
599			`r_bstrr <= i_bstrr;`
600			`end`
601			`end`
602
603			`always @(posedge clk_core) begin`
604			`r_brid <= i_brid;`
605			`r_bdbr <= i_bdbr;`
606			`end`
607
608			`always @(posedge clk_core or negedge rst_x) begin`
609			`if (~rst_x) begin`
610			`r_back <= 1'b0;`
611			`r_backw <= 1'b0;`
612			`end else begin`
613			`r_back <= i_back;`
614			`r_backw <= i_backw;`
615			`end`
616			`end`
617
618			`// read data strobe & outout (Read Only Port)`
619			`always @(posedge clk_core or negedge rst_x) begin`
620			`if (~rst_x) begin`
621			`r_strr2 <= 1'b0;`
622			`end else begin`
623			`r_strr2 <= w_strr2;`
624			`end`
625			`end`
626
627			`always @(posedge clk_core) begin`
628			`r_dbr2 <= w_dbr2;`
629			`end`
630
631			`/////////////////////////`
632			`// module instantiation`
633			`/////////////////////////`
634			`// read data priority fifo`
635			`// contain port number + burst length`
636			`wire [7:0] w_dnum;`
637			`wire w_empty;`
638			`ifdef USE_THREAD
639			`else
640			`fm_cmn_bfifo #(2+P_IB_LEN_WIDTH,7) fifo (`
641			`.clk_core(clk_core),`
642			`.rst_x(rst_x),`
643			`.i_wstrobe(w_fifo_write),`
644			`.i_dt(w_fifo_din),`
645			`.o_full(w_fifo_full),`
646			`.i_renable(w_read_end),`
647			`.o_dt(w_fifo_dout),`
648			`.o_empty(w_empty),`
649			`.o_dnum(w_dnum)`
650			`);`
651			`endif
652
653
654			`wire w_error;`
655			`assign w_error = w_empty & r_bstrr;`
656
657			`reg [15:0] r_req_cnt;`
658			`reg [15:0] r_acc_cnt;`
659
660			`always @(posedge clk_core or negedge rst_x) begin`
661			`if (~rst_x) begin`
662			`r_req_cnt <= 'd0;`
663			`r_acc_cnt <= 'd0;`
664			`end else begin`
665			`if (w_fifo_write) r_req_cnt <= r_req_cnt + w_len;`
666			`if (i_bstrr) r_acc_cnt <= r_acc_cnt + 1'b1;`
667
668			`end`
669			`end`
670			`endmodule`