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//=======================================================================
// Project Monophony
//   Wire-Frame 3D Graphics Accelerator IP Core
//
// File:
//   fm_geo_mem.v
//
// Abstract:
//   Geometry Engine memory controller.
//
// Author:
//   Kenji Ishimaru (info.info.wf3d@gmail.com)
//
//======================================================================
//
// Copyright (c) 2015, Kenji Ishimaru
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//  -Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//  -Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
 
`include "fm_3d_define.v"
module fm_geo_mem (
  // system
  input         clk_core,
  input         rst_x,
  output        o_state,
  // Vertex Fetch Memory I/F (Read Only)
(* mark_debug = "true" *)  output        o_req_m,
(* mark_debug = "true" *)    output [31:0] o_adrs_m,
(* mark_debug = "true" *)    output [2:0]  o_len_m,
(* mark_debug = "true" *)    input         i_ack_m,
(* mark_debug = "true" *)    input         i_strr_m,
(* mark_debug = "true" *)    input  [31:0] i_dbr_m,
  // Register Configuration
  //   vertex fetch
(* mark_debug = "true" *)    input         i_dma_start,
(* mark_debug = "true" *)    input  [29:0] i_dma_top_address,
(* mark_debug = "true" *)    input  [15:0] i_dma_size,
(* mark_debug = "true" *)    output        o_dma_end,
  // vertex output
(* mark_debug = "true" *)    output        o_en,
(* mark_debug = "true" *)    input         i_ack,
(* mark_debug = "true" *)    output [21:0] o_vx,
(* mark_debug = "true" *)    output [21:0] o_vy,
(* mark_debug = "true" *)    output [21:0] o_vz,
(* mark_debug = "true" *)    output [21:0] o_vw
);
parameter P_BURST_MODE = 0;
localparam P_IDLE  = 'd0;
localparam P_REQ   = 'd1;
localparam P_RD_X  = 'd2;
localparam P_RD_Y  = 'd3;
localparam P_RD_Z  = 'd4;
localparam P_RD_W  = 'd5;
localparam P_ACK_WAIT = 'd6;
localparam P_DONE  = 'd7;
 
//////////////////////////////////
// reg
//////////////////////////////////
(* mark_debug = "true" *) reg [2:0]       r_state;
reg [21:0]      r_vx;
reg [21:0]      r_vy;
reg [21:0]      r_vz;
reg [15:0]      r_size;
reg [29:0]      r_cur_adrs;
//////////////////////////////////
// wire
//////////////////////////////////
wire        w_set_adrs;
wire [21:0] w_adrs;
wire        w_read_end;
wire [21:0] w_f22;
//////////////////////////////////
// assign
//////////////////////////////////
assign o_state = (r_state == P_IDLE);
assign o_len_m = 3'd3;   // x,y,z
generate
if (P_BURST_MODE == 1) begin
  assign o_req_m = (r_state == P_REQ);
end else begin
  assign o_req_m = (r_state == P_RD_X) |
                   (r_state == P_RD_Y) |
                   (r_state == P_RD_Z) ;
end
endgenerate
 
assign w_read_end = (r_size == i_dma_size);
assign o_adrs_m = {r_cur_adrs,2'b0};  // 1 size = 3*4bytes
assign o_dma_end = (r_state == P_DONE);
assign o_en = (r_state == P_ACK_WAIT);
 
assign o_vx = r_vx;
assign o_vy = r_vy;
assign o_vz = r_vz;
assign o_vw = 22'hf8000;  // 1.0
//assign o_vw = r_vw;  // 1.0
//////////////////////////////////
// always
//////////////////////////////////
generate
if (P_BURST_MODE == 1) begin
`ifdef D3D_SYNC_RESET
  always @(posedge clk_core) begin
`else
  always @(posedge clk_core or negedge rst_x) begin
`endif
    if (rst_x == `D3D_RESET_POL) begin
      r_state <= P_IDLE;
      r_size <= 16'h0;
      r_cur_adrs <= 20'h0;
    end else begin
      case (r_state)
        P_IDLE: begin
          if (i_dma_start) begin
            r_size <= 16'h0;
            r_cur_adrs <= i_dma_top_address;
            r_state <= P_REQ;
          end
        end
        P_REQ: begin
          if (i_ack_m) begin
            r_size <= r_size + 2'd3;  // 1 means a sets of (x,y,z, not including w)
            r_cur_adrs <= r_cur_adrs + 2'd3;
            r_state <= P_RD_X;
          end
        end
        P_RD_X: begin
          if (i_strr_m) r_state <= P_RD_Y;
        end
        P_RD_Y: begin
          if (i_strr_m) r_state <= P_RD_Z;
        end
        P_RD_Z: begin
          if (i_strr_m) r_state <= P_ACK_WAIT;
        end
        P_ACK_WAIT: begin  // next transfer
          if (i_ack) begin  // outgoint data ack
            if (w_read_end) r_state <= P_DONE;
            else r_state <= P_REQ;
          end
        end
        P_DONE: begin
          if (~i_dma_start) r_state <= P_IDLE;
        end
      endcase
    end
  end
 
  always @(posedge clk_core) begin
    case (r_state)
      P_RD_X: begin
        if (i_strr_m) r_vx <= w_f22;
      end
      P_RD_Y: begin
        if (i_strr_m) r_vy <= w_f22;
      end
      P_RD_Z: begin
        if (i_strr_m) r_vz <= w_f22;
      end
    endcase
  end
end else begin
   // single access mode
`ifdef D3D_SYNC_RESET
  always @(posedge clk_core) begin
`else
  always @(posedge clk_core or negedge rst_x) begin
`endif
    if (rst_x == `D3D_RESET_POL) begin
      r_state <= P_IDLE;
      r_size <= 16'h0;
      r_cur_adrs <= 30'h0;
    end else begin
      case (r_state)
        P_IDLE: begin
          if (i_dma_start) begin
            r_size <= 16'h0;
            r_cur_adrs <= i_dma_top_address;
            r_state <= P_RD_X;
          end
        end
        P_RD_X: begin
          if (i_ack_m) begin
            r_size <= r_size + 2'd1;
            r_cur_adrs <= r_cur_adrs + 2'd1;
            r_state <= P_RD_Y;
          end
        end
        P_RD_Y: begin
          if (i_ack_m) begin
            r_size <= r_size + 2'd1;
            r_cur_adrs <= r_cur_adrs + 2'd1;
            r_state <= P_RD_Z;
          end
        end
        P_RD_Z: begin
          if (i_ack_m) begin
            r_size <= r_size + 2'd1;
            r_cur_adrs <= r_cur_adrs + 2'd1;
            r_state <= P_ACK_WAIT;
          end
        end
        P_ACK_WAIT: begin
          if (i_ack) begin
            if (w_read_end) r_state <= P_DONE;
            else r_state <= P_RD_X;
          end
        end
        P_DONE: begin
          if (~i_dma_start) r_state <= P_IDLE;
        end
      endcase
    end
  end
 
  always @(posedge clk_core) begin
    case (r_state)
      P_RD_X: begin
        if (i_ack_m) r_vx <= w_f22;
      end
      P_RD_Y: begin
        if (i_ack_m) r_vy <= w_f22;
      end
      P_RD_Z: begin
        if (i_ack_m) r_vz <= w_f22;
      end
    endcase
  end
end
endgenerate
 
 
// float cpnversion
fm_3d_fcnv u_float_fcnv (
  .i_f32(i_dbr_m),
  .o_f22(w_f22)
);
 
endmodule

Line No.	Rev	Author	Line
1	2	specular	`//=======================================================================`
2			`// Project Monophony`
3			`// Wire-Frame 3D Graphics Accelerator IP Core`
4			`//`
5			`// File:`
6			`// fm_geo_mem.v`
7			`//`
8			`// Abstract:`
9			`// Geometry Engine memory controller.`
10			`//`
11			`// Author:`
12	9	specular	`// Kenji Ishimaru (info.info.wf3d@gmail.com)`
13	2	specular	`//`
14			`//======================================================================`
15			`//`
16			`// Copyright (c) 2015, Kenji Ishimaru`
17			`// All rights reserved.`
18			`//`
19			`// Redistribution and use in source and binary forms, with or without`
20			`// modification, are permitted provided that the following conditions are met:`
21			`//`
22			`// -Redistributions of source code must retain the above copyright notice,`
23			`// this list of conditions and the following disclaimer.`
24			`// -Redistributions in binary form must reproduce the above copyright notice,`
25			`// this list of conditions and the following disclaimer in the documentation`
26			`// and/or other materials provided with the distribution.`
27			`//`
28			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
29			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
30			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
31			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR`
32			`// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,`
33			`// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,`
38			`// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`//`
40			`// Revision History`
41
42			`include "fm_3d_define.v"
43			`module fm_geo_mem (`
44			`// system`
45			`input clk_core,`
46			`input rst_x,`
47			`output o_state,`
48			`// Vertex Fetch Memory I/F (Read Only)`
49	4	specular	`(* mark_debug = "true" *) output o_req_m,`
50			`(* mark_debug = "true" *) output [31:0] o_adrs_m,`
51			`(* mark_debug = "true" *) output [2:0] o_len_m,`
52			`(* mark_debug = "true" *) input i_ack_m,`
53			`(* mark_debug = "true" *) input i_strr_m,`
54			`(* mark_debug = "true" *) input [31:0] i_dbr_m,`
55	2	specular	`// Register Configuration`
56			`// vertex fetch`
57	4	specular	`(* mark_debug = "true" *) input i_dma_start,`
58			`(* mark_debug = "true" *) input [29:0] i_dma_top_address,`
59			`(* mark_debug = "true" *) input [15:0] i_dma_size,`
60			`(* mark_debug = "true" *) output o_dma_end,`
61	2	specular	`// vertex output`
62	4	specular	`(* mark_debug = "true" *) output o_en,`
63			`(* mark_debug = "true" *) input i_ack,`
64			`(* mark_debug = "true" *) output [21:0] o_vx,`
65			`(* mark_debug = "true" *) output [21:0] o_vy,`
66			`(* mark_debug = "true" *) output [21:0] o_vz,`
67			`(* mark_debug = "true" *) output [21:0] o_vw`
68	2	specular	`);`
69			`parameter P_BURST_MODE = 0;`
70			`localparam P_IDLE = 'd0;`
71			`localparam P_REQ = 'd1;`
72			`localparam P_RD_X = 'd2;`
73			`localparam P_RD_Y = 'd3;`
74			`localparam P_RD_Z = 'd4;`
75			`localparam P_RD_W = 'd5;`
76			`localparam P_ACK_WAIT = 'd6;`
77			`localparam P_DONE = 'd7;`
78
79			`//////////////////////////////////`
80			`// reg`
81			`//////////////////////////////////`
82	4	specular	`(* mark_debug = "true" *) reg [2:0] r_state;`
83	2	specular	`reg [21:0] r_vx;`
84			`reg [21:0] r_vy;`
85			`reg [21:0] r_vz;`
86			`reg [15:0] r_size;`
87			`reg [29:0] r_cur_adrs;`
88			`//////////////////////////////////`
89			`// wire`
90			`//////////////////////////////////`
91			`wire w_set_adrs;`
92			`wire [21:0] w_adrs;`
93			`wire w_read_end;`
94			`wire [21:0] w_f22;`
95			`//////////////////////////////////`
96			`// assign`
97			`//////////////////////////////////`
98			`assign o_state = (r_state == P_IDLE);`
99			`assign o_len_m = 3'd3; // x,y,z`
100			`generate`
101			`if (P_BURST_MODE == 1) begin`
102			`assign o_req_m = (r_state == P_REQ);`
103			`end else begin`
104			`assign o_req_m = (r_state == P_RD_X) \|`
105			`(r_state == P_RD_Y) \|`
106			`(r_state == P_RD_Z) ;`
107			`end`
108			`endgenerate`
109
110			`assign w_read_end = (r_size == i_dma_size);`
111			`assign o_adrs_m = {r_cur_adrs,2'b0}; // 1 size = 3*4bytes`
112			`assign o_dma_end = (r_state == P_DONE);`
113			`assign o_en = (r_state == P_ACK_WAIT);`
114
115			`assign o_vx = r_vx;`
116			`assign o_vy = r_vy;`
117			`assign o_vz = r_vz;`
118			`assign o_vw = 22'hf8000; // 1.0`
119			`//assign o_vw = r_vw; // 1.0`
120			`//////////////////////////////////`
121			`// always`
122			`//////////////////////////////////`
123			`generate`
124			`if (P_BURST_MODE == 1) begin`
125			`ifdef D3D_SYNC_RESET
126			`always @(posedge clk_core) begin`
127			`else
128			`always @(posedge clk_core or negedge rst_x) begin`
129			`endif
130			if (rst_x == `D3D_RESET_POL) begin
131			`r_state <= P_IDLE;`
132			`r_size <= 16'h0;`
133			`r_cur_adrs <= 20'h0;`
134			`end else begin`
135			`case (r_state)`
136			`P_IDLE: begin`
137			`if (i_dma_start) begin`
138			`r_size <= 16'h0;`
139			`r_cur_adrs <= i_dma_top_address;`
140			`r_state <= P_REQ;`
141			`end`
142			`end`
143			`P_REQ: begin`
144			`if (i_ack_m) begin`
145			`r_size <= r_size + 2'd3; // 1 means a sets of (x,y,z, not including w)`
146			`r_cur_adrs <= r_cur_adrs + 2'd3;`
147			`r_state <= P_RD_X;`
148			`end`
149			`end`
150			`P_RD_X: begin`
151			`if (i_strr_m) r_state <= P_RD_Y;`
152			`end`
153			`P_RD_Y: begin`
154			`if (i_strr_m) r_state <= P_RD_Z;`
155			`end`
156			`P_RD_Z: begin`
157			`if (i_strr_m) r_state <= P_ACK_WAIT;`
158			`end`
159			`P_ACK_WAIT: begin // next transfer`
160			`if (i_ack) begin // outgoint data ack`
161			`if (w_read_end) r_state <= P_DONE;`
162			`else r_state <= P_REQ;`
163			`end`
164			`end`
165			`P_DONE: begin`
166			`if (~i_dma_start) r_state <= P_IDLE;`
167			`end`
168			`endcase`
169			`end`
170			`end`
171
172			`always @(posedge clk_core) begin`
173			`case (r_state)`
174			`P_RD_X: begin`
175			`if (i_strr_m) r_vx <= w_f22;`
176			`end`
177			`P_RD_Y: begin`
178			`if (i_strr_m) r_vy <= w_f22;`
179			`end`
180			`P_RD_Z: begin`
181			`if (i_strr_m) r_vz <= w_f22;`
182			`end`
183			`endcase`
184			`end`
185			`end else begin`
186			`// single access mode`
187			`ifdef D3D_SYNC_RESET
188			`always @(posedge clk_core) begin`
189			`else
190			`always @(posedge clk_core or negedge rst_x) begin`
191			`endif
192			if (rst_x == `D3D_RESET_POL) begin
193			`r_state <= P_IDLE;`
194			`r_size <= 16'h0;`
195			`r_cur_adrs <= 30'h0;`
196			`end else begin`
197			`case (r_state)`
198			`P_IDLE: begin`
199			`if (i_dma_start) begin`
200			`r_size <= 16'h0;`
201			`r_cur_adrs <= i_dma_top_address;`
202			`r_state <= P_RD_X;`
203			`end`
204			`end`
205			`P_RD_X: begin`
206			`if (i_ack_m) begin`
207			`r_size <= r_size + 2'd1;`
208			`r_cur_adrs <= r_cur_adrs + 2'd1;`
209			`r_state <= P_RD_Y;`
210			`end`
211			`end`
212			`P_RD_Y: begin`
213			`if (i_ack_m) begin`
214			`r_size <= r_size + 2'd1;`
215			`r_cur_adrs <= r_cur_adrs + 2'd1;`
216			`r_state <= P_RD_Z;`
217			`end`
218			`end`
219			`P_RD_Z: begin`
220			`if (i_ack_m) begin`
221			`r_size <= r_size + 2'd1;`
222			`r_cur_adrs <= r_cur_adrs + 2'd1;`
223			`r_state <= P_ACK_WAIT;`
224			`end`
225			`end`
226			`P_ACK_WAIT: begin`
227			`if (i_ack) begin`
228			`if (w_read_end) r_state <= P_DONE;`
229			`else r_state <= P_RD_X;`
230			`end`
231			`end`
232			`P_DONE: begin`
233			`if (~i_dma_start) r_state <= P_IDLE;`
234			`end`
235			`endcase`
236			`end`
237			`end`
238
239			`always @(posedge clk_core) begin`
240			`case (r_state)`
241			`P_RD_X: begin`
242			`if (i_ack_m) r_vx <= w_f22;`
243			`end`
244			`P_RD_Y: begin`
245			`if (i_ack_m) r_vy <= w_f22;`
246			`end`
247			`P_RD_Z: begin`
248			`if (i_ack_m) r_vz <= w_f22;`
249			`end`
250			`endcase`
251			`end`
252			`end`
253			`endgenerate`
254
255
256			`// float cpnversion`
257			`fm_3d_fcnv u_float_fcnv (`
258			`.i_f32(i_dbr_m),`
259			`.o_f22(w_f22)`
260			`);`
261
262			`endmodule`

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[/] [wf3d/] [trunk/] [rtl/] [core/] [fm_geo_mem.v] - Blame information for rev 9