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[/] [wf3d/] [trunk/] [rtl/] [core/] [fm_ras_line.v] - Blame information for rev 9

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//=======================================================================
// Project Monophony
//   Wire-Frame 3D Graphics Accelerator IP Core
//
// File:
//   fm_ras_line.v
//
// Abstract:
//   Line Rasterization. DDA.
//
// Author:
//   Kenji Ishimaru (info.info.wf3d@gmail.com)
//
//======================================================================
//
// Copyright (c) 2015, Kenji Ishimaru
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//  -Redistributions of source code must retain the above copyright notice,
//   this list of conditions and the following disclaimer.
//  -Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Revision History
 
`include "fm_3d_define.v"
module fm_ras_line (
  // system
  input         clk_core,
  input         rst_x,
  output        o_state,
  // Register Configuration
  input [15:0] i_scr_w_m1,  // Screen Width-1
  input [15:0] i_scr_h_m1,  // Screen Height-1
  //   // Vertex input
  input         i_en,
  output        o_ack,
  input  [`D3D_FTOI_WIDTH-1:0] i_v0_x,
  input  [`D3D_FTOI_WIDTH-1:0] i_v0_y,
  input  [`D3D_FTOI_WIDTH-1:0] i_v1_x,
  input  [`D3D_FTOI_WIDTH-1:0] i_v1_y,
  // Pixel out
  output        o_en,
  input         i_ack,
  output [`D3D_FTOI_WIDTH-1:0]  o_x,
  output [`D3D_FTOI_WIDTH-1:0]  o_y
);
localparam P_IDLE = 'd0;
localparam P_OUT   = 'd1;
localparam P_PROC = 'd2;
 
//////////////////////////////////
// reg
//////////////////////////////////
reg [`D3D_FTOI_WIDTH-1:0] r_x0;
reg [`D3D_FTOI_WIDTH-1:0] r_y0;
reg [`D3D_FTOI_WIDTH-1:0] r_x1;
reg [`D3D_FTOI_WIDTH-1:0] r_y1;
reg [1:0]  r_state;
reg [`D3D_FTOI_WIDTH-1:0] r_x;
reg [`D3D_FTOI_WIDTH-1:0] r_y;
reg [`D3D_FTOI_WIDTH-1:0] r_err;
reg [`D3D_FTOI_WIDTH-1:0] r_e2;
//////////////////////////////////
// wire
//////////////////////////////////
wire [`D3D_FTOI_WIDTH-1:0] w_x0;
wire [`D3D_FTOI_WIDTH-1:0] w_y0;
wire [`D3D_FTOI_WIDTH-1:0] w_x1;
wire [`D3D_FTOI_WIDTH-1:0] w_y1;
wire [`D3D_FTOI_WIDTH-1:0] w_dx;
wire [`D3D_FTOI_WIDTH-1:0] w_dy;
wire [`D3D_FTOI_WIDTH-1:0] w_dym;
wire w_sx_flag;
wire w_sy_flag;
wire [`D3D_FTOI_WIDTH-1:0] w_err;
wire [`D3D_FTOI_WIDTH-1:0] w_e2;
wire w_gte_flag;
wire w_lte_flag;
wire w_reject;
wire w_end;
//////////////////////////////////
// assign
//////////////////////////////////
assign o_state = (r_state == P_IDLE);
assign w_x0 = (r_state == P_IDLE) ? i_v0_x : r_x0;
assign w_y0 = (r_state == P_IDLE) ? i_v0_y : r_y0;
assign w_x1 = (r_state == P_IDLE) ? i_v1_x : r_x1;
assign w_y1 = (r_state == P_IDLE) ? i_v1_y : r_y1;
 
assign w_sx_flag = (w_x0[`D3D_FTOI_WIDTH-1]) ? 1'b1 :
                   (w_x1[`D3D_FTOI_WIDTH-1]) ? 1'b0 :
                    w_x0 < w_x1;  // x0 < x1
assign w_sy_flag = (w_y0[`D3D_FTOI_WIDTH-1]) ? 1'b1 :
                   (w_y1[`D3D_FTOI_WIDTH-1]) ? 1'b0 :
                   w_y0 < w_y1;  // y0 < y1
 
assign w_dx = (w_sx_flag) ? w_x1 - w_x0 : w_x0 - w_x1;
assign w_dy = (w_sy_flag) ? w_y1 - w_y0 : w_y0 - w_y1;
assign w_dym = ~w_dy + 1'b1;
 
assign w_err = w_dx + w_dym;
 
assign o_ack = (r_state == P_IDLE);
assign o_en = (r_state == P_OUT) & (!w_reject);
assign w_end = (r_x == w_x1)&(r_y == w_y1);
assign w_e2 = r_err << 1;
assign o_x = r_x;
assign o_y = r_y;
 
assign w_gte_flag = f_gte(r_e2,w_dym);
assign w_lte_flag = f_lte(r_e2,w_dx);
 
assign w_reject = r_x[`D3D_FTOI_WIDTH-1] | r_y[`D3D_FTOI_WIDTH-1] |  // negative value
                  (r_x[`D3D_FTOI_WIDTH-2:0] > i_scr_w_m1)|
                  (r_y[`D3D_FTOI_WIDTH-2:0] > i_scr_h_m1);  // size over
//////////////////////////////////
// always
//////////////////////////////////
`ifdef D3D_SYNC_RESET
always @(posedge clk_core) begin
`else
always @(posedge clk_core or negedge rst_x) begin
`endif
  if (rst_x == `D3D_RESET_POL) begin
    r_state <= P_IDLE;
  end else begin
    case (r_state)
      P_IDLE: begin
        if (i_en) r_state <= P_OUT;
      end
      P_OUT: begin
        if (i_ack|w_reject) begin
          if (w_end) r_state <= P_IDLE;
          else r_state <= P_PROC;
        end
      end
      P_PROC: begin
        r_state <= P_OUT;
      end
    endcase
  end
end
 
always @(posedge clk_core) begin
  case (r_state)
    P_IDLE: begin
      r_x0 <= i_v0_x;
      r_y0 <= i_v0_y;
      r_x1 <= i_v1_x;
      r_y1 <= i_v1_y;
      r_x <= i_v0_x;
      r_y <= i_v0_y;
      r_err <= w_err;
    end
    P_OUT: begin
      if (i_ack|w_reject) begin
        r_e2 <= w_e2;
      end
    end
    P_PROC: begin
      case ({w_gte_flag,w_lte_flag})
        2'b01: begin
          r_err <= r_err + w_dx;
          r_y <= (w_sy_flag) ? r_y + 1'b1 : r_y - 1'b1;
        end
        2'b10: begin
          r_err <= r_err + w_dym;
          r_x <= (w_sx_flag) ? r_x + 1'b1 : r_x - 1'b1;
        end
        2'b11: begin
          r_err <= r_err + w_err;
          r_y <= (w_sy_flag) ? r_y + 1'b1 : r_y - 1'b1;
          r_x <= (w_sx_flag) ? r_x + 1'b1 : r_x - 1'b1;
        end
      endcase
    end
  endcase
end
 
// ia >= i_b ?
function f_gte;
  input [`D3D_FTOI_WIDTH-1:0] i_a;
  input [`D3D_FTOI_WIDTH-1:0] i_b;
  reg result;
  reg sign_a,sign_b;
  begin
    result = 0;
    sign_a = i_a[`D3D_FTOI_WIDTH-1];
    sign_b = i_b[`D3D_FTOI_WIDTH-1];
    case ({sign_a,sign_b})
      2'b00: begin
        // a >= 0, b >= 0
        if (i_a[`D3D_FTOI_WIDTH-2:0] >= i_b[`D3D_FTOI_WIDTH-2:0]) result = 1'b1;
        else result = 1'b0;
      end
      2'b01: begin
        // a >= 0, b < 0
        result = 1'b1;
      end
      2'b10: begin
        // a < 0, b >= 0
        result = 1'b0;
      end
      2'b11: begin
        // a < 0, b < 0
        if (i_a >= i_b) result = 1'b1;
        else result = 1'b0;
      end
    endcase
    f_gte = result;
  end
endfunction
 
// ia <= i_b ?
function f_lte;
  input [`D3D_FTOI_WIDTH-1:0] i_a;
  input [`D3D_FTOI_WIDTH-1:0] i_b;
  reg result;
  reg sign_a,sign_b;
  begin
    result = 0;
    sign_a = i_a[`D3D_FTOI_WIDTH-1];
    sign_b = i_b[`D3D_FTOI_WIDTH-1];
    case ({sign_a,sign_b})
      2'b00: begin
        // a >= 0, b >= 0
        if (i_a <= i_b) result = 1'b1;
        else result = 1'b0;
      end
      2'b01: begin
        // a >= 0, b < 0
        result = 1'b0;
      end
      2'b10: begin
        // a < 0, b >= 1
        result = 1'b1;
      end
      2'b11: begin
        // a < 0, b < 0
        if (i_a <= i_b) result = 1'b1;
        else result = 1'b0;
      end
    endcase
    f_lte = result;
  end
endfunction
 
`ifdef RTL_DEBUG
integer line_no;
initial line_no = 0;
    always @(posedge clk_core) begin
      if (i_en & o_ack) begin
         $display("Line No. %d : x0,y0 x1,y1 = %d %d %d %d",line_no, i_v0_x,i_v0_y,i_v1_x,i_v1_y);
         line_no = line_no + 1;
      end
    end
`endif
endmodule

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[/] [wf3d/] [trunk/] [rtl/] [core/] [fm_ras_line.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	2	specular	`//=======================================================================`
2			`// Project Monophony`
3			`// Wire-Frame 3D Graphics Accelerator IP Core`
4			`//`
5			`// File:`
6			`// fm_ras_line.v`
7			`//`
8			`// Abstract:`
9			`// Line Rasterization. DDA.`
10			`//`
11			`// Author:`
12	9	specular	`// Kenji Ishimaru (info.info.wf3d@gmail.com)`
13	2	specular	`//`
14			`//======================================================================`
15			`//`
16			`// Copyright (c) 2015, Kenji Ishimaru`
17			`// All rights reserved.`
18			`//`
19			`// Redistribution and use in source and binary forms, with or without`
20			`// modification, are permitted provided that the following conditions are met:`
21			`//`
22			`// -Redistributions of source code must retain the above copyright notice,`
23			`// this list of conditions and the following disclaimer.`
24			`// -Redistributions in binary form must reproduce the above copyright notice,`
25			`// this list of conditions and the following disclaimer in the documentation`
26			`// and/or other materials provided with the distribution.`
27			`//`
28			`// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
29			`// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,`
30			`// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR`
31			`// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR`
32			`// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,`
33			`// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,`
38			`// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`//`
40			`// Revision History`
41
42			`include "fm_3d_define.v"
43			`module fm_ras_line (`
44			`// system`
45			`input clk_core,`
46			`input rst_x,`
47			`output o_state,`
48			`// Register Configuration`
49			`input [15:0] i_scr_w_m1, // Screen Width-1`
50			`input [15:0] i_scr_h_m1, // Screen Height-1`
51			`// // Vertex input`
52			`input i_en,`
53			`output o_ack,`
54			input [`D3D_FTOI_WIDTH-1:0] i_v0_x,
55			input [`D3D_FTOI_WIDTH-1:0] i_v0_y,
56			input [`D3D_FTOI_WIDTH-1:0] i_v1_x,
57			input [`D3D_FTOI_WIDTH-1:0] i_v1_y,
58			`// Pixel out`
59			`output o_en,`
60			`input i_ack,`
61			output [`D3D_FTOI_WIDTH-1:0] o_x,
62			output [`D3D_FTOI_WIDTH-1:0] o_y
63			`);`
64			`localparam P_IDLE = 'd0;`
65			`localparam P_OUT = 'd1;`
66			`localparam P_PROC = 'd2;`
67
68			`//////////////////////////////////`
69			`// reg`
70			`//////////////////////////////////`
71			reg [`D3D_FTOI_WIDTH-1:0] r_x0;
72			reg [`D3D_FTOI_WIDTH-1:0] r_y0;
73			reg [`D3D_FTOI_WIDTH-1:0] r_x1;
74			reg [`D3D_FTOI_WIDTH-1:0] r_y1;
75			`reg [1:0] r_state;`
76			reg [`D3D_FTOI_WIDTH-1:0] r_x;
77			reg [`D3D_FTOI_WIDTH-1:0] r_y;
78			reg [`D3D_FTOI_WIDTH-1:0] r_err;
79			reg [`D3D_FTOI_WIDTH-1:0] r_e2;
80			`//////////////////////////////////`
81			`// wire`
82			`//////////////////////////////////`
83			wire [`D3D_FTOI_WIDTH-1:0] w_x0;
84			wire [`D3D_FTOI_WIDTH-1:0] w_y0;
85			wire [`D3D_FTOI_WIDTH-1:0] w_x1;
86			wire [`D3D_FTOI_WIDTH-1:0] w_y1;
87			wire [`D3D_FTOI_WIDTH-1:0] w_dx;
88			wire [`D3D_FTOI_WIDTH-1:0] w_dy;
89			wire [`D3D_FTOI_WIDTH-1:0] w_dym;
90			`wire w_sx_flag;`
91			`wire w_sy_flag;`
92			wire [`D3D_FTOI_WIDTH-1:0] w_err;
93			wire [`D3D_FTOI_WIDTH-1:0] w_e2;
94			`wire w_gte_flag;`
95			`wire w_lte_flag;`
96			`wire w_reject;`
97			`wire w_end;`
98			`//////////////////////////////////`
99			`// assign`
100			`//////////////////////////////////`
101			`assign o_state = (r_state == P_IDLE);`
102			`assign w_x0 = (r_state == P_IDLE) ? i_v0_x : r_x0;`
103			`assign w_y0 = (r_state == P_IDLE) ? i_v0_y : r_y0;`
104			`assign w_x1 = (r_state == P_IDLE) ? i_v1_x : r_x1;`
105			`assign w_y1 = (r_state == P_IDLE) ? i_v1_y : r_y1;`
106
107			assign w_sx_flag = (w_x0[`D3D_FTOI_WIDTH-1]) ? 1'b1 :
108			(w_x1[`D3D_FTOI_WIDTH-1]) ? 1'b0 :
109			`w_x0 < w_x1; // x0 < x1`
110			assign w_sy_flag = (w_y0[`D3D_FTOI_WIDTH-1]) ? 1'b1 :
111			(w_y1[`D3D_FTOI_WIDTH-1]) ? 1'b0 :
112			`w_y0 < w_y1; // y0 < y1`
113
114			`assign w_dx = (w_sx_flag) ? w_x1 - w_x0 : w_x0 - w_x1;`
115			`assign w_dy = (w_sy_flag) ? w_y1 - w_y0 : w_y0 - w_y1;`
116			`assign w_dym = ~w_dy + 1'b1;`
117
118			`assign w_err = w_dx + w_dym;`
119
120			`assign o_ack = (r_state == P_IDLE);`
121			`assign o_en = (r_state == P_OUT) & (!w_reject);`
122			`assign w_end = (r_x == w_x1)&(r_y == w_y1);`
123			`assign w_e2 = r_err << 1;`
124			`assign o_x = r_x;`
125			`assign o_y = r_y;`
126
127			`assign w_gte_flag = f_gte(r_e2,w_dym);`
128			`assign w_lte_flag = f_lte(r_e2,w_dx);`
129
130			assign w_reject = r_x[`D3D_FTOI_WIDTH-1] \| r_y[`D3D_FTOI_WIDTH-1] \| // negative value
131			(r_x[`D3D_FTOI_WIDTH-2:0] > i_scr_w_m1)\|
132			(r_y[`D3D_FTOI_WIDTH-2:0] > i_scr_h_m1); // size over
133			`//////////////////////////////////`
134			`// always`
135			`//////////////////////////////////`
136			`ifdef D3D_SYNC_RESET
137			`always @(posedge clk_core) begin`
138			`else
139			`always @(posedge clk_core or negedge rst_x) begin`
140			`endif
141			if (rst_x == `D3D_RESET_POL) begin
142			`r_state <= P_IDLE;`
143			`end else begin`
144			`case (r_state)`
145			`P_IDLE: begin`
146			`if (i_en) r_state <= P_OUT;`
147			`end`
148			`P_OUT: begin`
149			`if (i_ack\|w_reject) begin`
150			`if (w_end) r_state <= P_IDLE;`
151			`else r_state <= P_PROC;`
152			`end`
153			`end`
154			`P_PROC: begin`
155			`r_state <= P_OUT;`
156			`end`
157			`endcase`
158			`end`
159			`end`
160
161			`always @(posedge clk_core) begin`
162			`case (r_state)`
163			`P_IDLE: begin`
164			`r_x0 <= i_v0_x;`
165			`r_y0 <= i_v0_y;`
166			`r_x1 <= i_v1_x;`
167			`r_y1 <= i_v1_y;`
168			`r_x <= i_v0_x;`
169			`r_y <= i_v0_y;`
170			`r_err <= w_err;`
171			`end`
172			`P_OUT: begin`
173			`if (i_ack\|w_reject) begin`
174			`r_e2 <= w_e2;`
175			`end`
176			`end`
177			`P_PROC: begin`
178			`case ({w_gte_flag,w_lte_flag})`
179			`2'b01: begin`
180			`r_err <= r_err + w_dx;`
181			`r_y <= (w_sy_flag) ? r_y + 1'b1 : r_y - 1'b1;`
182			`end`
183			`2'b10: begin`
184			`r_err <= r_err + w_dym;`
185			`r_x <= (w_sx_flag) ? r_x + 1'b1 : r_x - 1'b1;`
186			`end`
187			`2'b11: begin`
188			`r_err <= r_err + w_err;`
189			`r_y <= (w_sy_flag) ? r_y + 1'b1 : r_y - 1'b1;`
190			`r_x <= (w_sx_flag) ? r_x + 1'b1 : r_x - 1'b1;`
191			`end`
192			`endcase`
193			`end`
194			`endcase`
195			`end`
196
197			`// ia >= i_b ?`
198			`function f_gte;`
199			input [`D3D_FTOI_WIDTH-1:0] i_a;
200			input [`D3D_FTOI_WIDTH-1:0] i_b;
201			`reg result;`
202			`reg sign_a,sign_b;`
203			`begin`
204			`result = 0;`
205			sign_a = i_a[`D3D_FTOI_WIDTH-1];
206			sign_b = i_b[`D3D_FTOI_WIDTH-1];
207			`case ({sign_a,sign_b})`
208			`2'b00: begin`
209			`// a >= 0, b >= 0`
210			if (i_a[`D3D_FTOI_WIDTH-2:0] >= i_b[`D3D_FTOI_WIDTH-2:0]) result = 1'b1;
211			`else result = 1'b0;`
212			`end`
213			`2'b01: begin`
214			`// a >= 0, b < 0`
215			`result = 1'b1;`
216			`end`
217			`2'b10: begin`
218			`// a < 0, b >= 0`
219			`result = 1'b0;`
220			`end`
221			`2'b11: begin`
222			`// a < 0, b < 0`
223			`if (i_a >= i_b) result = 1'b1;`
224			`else result = 1'b0;`
225			`end`
226			`endcase`
227			`f_gte = result;`
228			`end`
229			`endfunction`
230
231			`// ia <= i_b ?`
232			`function f_lte;`
233			input [`D3D_FTOI_WIDTH-1:0] i_a;
234			input [`D3D_FTOI_WIDTH-1:0] i_b;
235			`reg result;`
236			`reg sign_a,sign_b;`
237			`begin`
238			`result = 0;`
239			sign_a = i_a[`D3D_FTOI_WIDTH-1];
240			sign_b = i_b[`D3D_FTOI_WIDTH-1];
241			`case ({sign_a,sign_b})`
242			`2'b00: begin`
243			`// a >= 0, b >= 0`
244			`if (i_a <= i_b) result = 1'b1;`
245			`else result = 1'b0;`
246			`end`
247			`2'b01: begin`
248			`// a >= 0, b < 0`
249			`result = 1'b0;`
250			`end`
251			`2'b10: begin`
252			`// a < 0, b >= 1`
253			`result = 1'b1;`
254			`end`
255			`2'b11: begin`
256			`// a < 0, b < 0`
257			`if (i_a <= i_b) result = 1'b1;`
258			`else result = 1'b0;`
259			`end`
260			`endcase`
261			`f_lte = result;`
262			`end`
263			`endfunction`
264
265			`ifdef RTL_DEBUG
266			`integer line_no;`
267			`initial line_no = 0;`
268			`always @(posedge clk_core) begin`
269			`if (i_en & o_ack) begin`
270			`$display("Line No. %d : x0,y0 x1,y1 = %d %d %d %d",line_no, i_v0_x,i_v0_y,i_v1_x,i_v1_y);`
271			`line_no = line_no + 1;`
272			`end`
273			`end`
274			`endif
275			`endmodule`