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//=======================================================================
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// Project Monophony
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// Wire-Frame 3D Graphics Accelerator IP Core
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//
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// File:
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// rand_delay_r.v
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//
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// Abstract:
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// Pipeline delay module with reset
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// parameters :
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// WIDTH data width (default value is 8)
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// NUM_DELAY number of delay cycle (default value is 8)
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//
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// Author:
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// Kenji Ishimaru (info.info.wf3d@gmail.com)
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//
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//======================================================================
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// -Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// -Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Revision History
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module rand_delay_r (
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clk_core,
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rst_x,
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i_en,
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i_delay,
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i_data,
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o_data
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);
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////////////////////////////
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// parameter
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////////////////////////////
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parameter P_WIDTH = 8;
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parameter P_NUM_DELAY = 8;
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////////////////////////////
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// I/O definition
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////////////////////////////
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input clk_core;
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input rst_x;
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input i_en;
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input [7:0] i_delay;
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input [P_WIDTH-1:0] i_data;
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output [P_WIDTH-1:0] o_data;
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////////////////////////////
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// reg
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////////////////////////////
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reg [P_WIDTH-1:0] r_delay[0:P_NUM_DELAY-1];
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////////////////////////////
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// assign
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////////////////////////////
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// in/out port connection
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assign o_data = (i_delay < P_NUM_DELAY) ? r_delay[i_delay] :
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r_delay[P_NUM_DELAY-1];
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////////////////////////////
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// always
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////////////////////////////
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always @(posedge clk_core) begin
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if (i_en) r_delay[0] <= i_data;
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end
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// delay register connection
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integer i;
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always @(posedge clk_core or negedge rst_x) begin
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if (!rst_x) begin
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if ( P_NUM_DELAY > 1 ) begin
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for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
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r_delay[i] <= 0;
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end
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end
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end else begin
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if ( P_NUM_DELAY > 1 ) begin
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for ( i = 1; i < P_NUM_DELAY; i = i + 1) begin
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if (i_en) r_delay[i] <= r_delay[i-1];
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end
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end
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end
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end
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endmodule
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