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[/] [wiegand_ctl/] [trunk/] [syn/] [altera/] [wiegand_tx/] [output_files/] [wiegand_tx_top.fit.smsg] - Blame information for rev 17

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Line No. Rev Author Line
1 17 jeaander 
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
2 
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
3 
Extra Info (176236): Started Fast Input/Output/OE register processing
4 
Extra Info (176237): Finished Fast Input/Output/OE register processing
5 
Extra Info (176238): Start inferring scan chains for DSP blocks
6 
Extra Info (176239): Inferring scan chains for DSP blocks is complete
7 
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
8 
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

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