Subversion Repositories wiegand_ctl

set tool_name "ModelSim-Altera (Verilog)"

set corner_file_list {

        {{"Slow -6 1.2V 85 Model"} {wiegand_tx_top_6_1200mv_85c_slow.vo wiegand_tx_top_6_1200mv_85c_v_slow.sdo}}

        {{"Slow -6 1.2V 0 Model"} {wiegand_tx_top_6_1200mv_0c_slow.vo wiegand_tx_top_6_1200mv_0c_v_slow.sdo}}

        {{"Fast -M 1.2V 0 Model"} {wiegand_tx_top_min_1200mv_0c_fast.vo wiegand_tx_top_min_1200mv_0c_v_fast.sdo}}

}