Subversion Repositories wiegand_ctl

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#

# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, the Altera Quartus II License Agreement,

# the Altera MegaCore Function License Agreement, or other

# applicable license agreement, including, without limitation,

# that your use is for the sole purpose of programming logic

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# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition

# Date created = 10:59:20  February 16, 2015

#

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#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               wiegand_tx_top_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

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set_global_assignment -name FAMILY "Cyclone IV GX"

set_global_assignment -name DEVICE auto

set_global_assignment -name TOP_LEVEL_ENTITY wiegand_tx_top

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:59:20  FEBRUARY 16, 2015"

set_global_assignment -name LAST_QUARTUS_VERSION 14.0

set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/wiegand_tx_top.v

set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/wiegand_defines.v

set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/wb_interface.v

set_global_assignment -name VERILOG_FILE ../../../rtl/verilog/fifos.v

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top