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jeaander |
//! **************************************************************************
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// Written by: Map P.20131013 on Mon Feb 16 11:08:35 2015
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//! **************************************************************************
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SCHEMATIC START;
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COMP "one_o" LOCATE = SITE "A2" LEVEL 1;
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COMP "zero_o" LOCATE = SITE "A3" LEVEL 1;
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TIMEGRP wb_clk_i = BEL "lock_cfg" BEL "full_dly" BEL "one_o" BEL "zero_o" BEL
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"word_out_0" BEL "word_out_1" BEL "word_out_2" BEL "word_out_3" BEL
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"word_out_4" BEL "word_out_5" BEL "word_out_6" BEL "word_out_7" BEL
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"word_out_8" BEL "word_out_9" BEL "word_out_10" BEL "word_out_11" BEL
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"word_out_12" BEL "word_out_13" BEL "word_out_14" BEL "word_out_15"
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BEL "word_out_16" BEL "word_out_17" BEL "word_out_18" BEL
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"word_out_19" BEL "word_out_20" BEL "word_out_21" BEL "word_out_22"
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BEL "word_out_23" BEL "word_out_24" BEL "word_out_25" BEL
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"word_out_26" BEL "word_out_27" BEL "word_out_28" BEL "word_out_29"
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BEL "word_out_30" BEL "word_out_31" BEL "p2pCnt_0" BEL "p2pCnt_1" BEL
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"p2pCnt_2" BEL "p2pCnt_3" BEL "p2pCnt_4" BEL "pulseCnt_0" BEL
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"pulseCnt_1" BEL "pulseCnt_2" BEL "pulseCnt_3" BEL "pulseCnt_4" BEL
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"pulseCnt_5" BEL "pulseCnt_6" BEL "pulseCnt_7" BEL "pulseCnt_8" BEL
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"pulseCnt_9" BEL "pulseCnt_10" BEL "pulseCnt_11" BEL "pulseCnt_12" BEL
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"pulseCnt_13" BEL "pulseCnt_14" BEL "pulseCnt_15" BEL "pulseCnt_16"
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BEL "pulseCnt_17" BEL "pulseCnt_18" BEL "pulseCnt_19" BEL
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"pulseCnt_20" BEL "pulseCnt_21" BEL "pulseCnt_22" BEL "pulseCnt_23"
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BEL "pulseCnt_24" BEL "pulseCnt_25" BEL "pulseCnt_26" BEL
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"pulseCnt_27" BEL "pulseCnt_28" BEL "pulseCnt_29" BEL "pulseCnt_30"
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BEL "pulseCnt_31" BEL "bitCount_0" BEL "bitCount_1" BEL "bitCount_2"
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BEL "bitCount_3" BEL "bitCount_4" BEL "bitCount_5" BEL "bitCount_6"
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BEL "bitCountReg_0" BEL "bitCountReg_1" BEL "bitCountReg_2" BEL
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"bitCountReg_3" BEL "bitCountReg_4" BEL "bitCountReg_5" BEL
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"bitCountReg_6" BEL "state_FSM_FFd3" BEL "state_FSM_FFd1" BEL
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"state_FSM_FFd2" BEL "wb_interface/pulsewidth_0" BEL
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"wb_interface/pulsewidth_1" BEL "wb_interface/pulsewidth_2" BEL
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"wb_interface/pulsewidth_3" BEL "wb_interface/pulsewidth_4" BEL
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"wb_interface/pulsewidth_5" BEL "wb_interface/pulsewidth_6" BEL
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"wb_interface/pulsewidth_7" BEL "wb_interface/pulsewidth_8" BEL
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"wb_interface/pulsewidth_9" BEL "wb_interface/pulsewidth_10" BEL
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"wb_interface/pulsewidth_11" BEL "wb_interface/pulsewidth_12" BEL
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"wb_interface/pulsewidth_13" BEL "wb_interface/pulsewidth_14" BEL
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"wb_interface/pulsewidth_15" BEL "wb_interface/pulsewidth_16" BEL
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"wb_interface/pulsewidth_17" BEL "wb_interface/pulsewidth_18" BEL
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"wb_interface/pulsewidth_19" BEL "wb_interface/pulsewidth_20" BEL
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"wb_interface/pulsewidth_21" BEL "wb_interface/pulsewidth_22" BEL
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"wb_interface/pulsewidth_23" BEL "wb_interface/pulsewidth_24" BEL
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"wb_interface/pulsewidth_25" BEL "wb_interface/pulsewidth_26" BEL
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"wb_interface/pulsewidth_27" BEL "wb_interface/pulsewidth_28" BEL
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"wb_interface/pulsewidth_29" BEL "wb_interface/pulsewidth_30" BEL
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"wb_interface/pulsewidth_31" BEL "wb_interface/size_8" BEL
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"wb_interface/size_7" BEL "wb_interface/p2p_31" BEL
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"wb_interface/p2p_30" BEL "wb_interface/p2p_29" BEL
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"wb_interface/p2p_28" BEL "wb_interface/p2p_27" BEL
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"wb_interface/p2p_26" BEL "wb_interface/p2p_25" BEL
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"wb_interface/p2p_24" BEL "wb_interface/p2p_23" BEL
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"wb_interface/p2p_22" BEL "wb_interface/p2p_21" BEL
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"wb_interface/p2p_20" BEL "wb_interface/p2p_19" BEL
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"wb_interface/p2p_18" BEL "wb_interface/p2p_17" BEL
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"wb_interface/p2p_16" BEL "wb_interface/p2p_15" BEL
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"wb_interface/p2p_14" BEL "wb_interface/p2p_13" BEL
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"wb_interface/p2p_12" BEL "wb_interface/p2p_11" BEL
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"wb_interface/p2p_10" BEL "wb_interface/p2p_9" BEL
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"wb_interface/p2p_8" BEL "wb_interface/p2p_7" BEL "wb_interface/p2p_6"
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BEL "wb_interface/p2p_5" BEL "wb_interface/p2p_4" BEL
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"wb_interface/p2p_3" BEL "wb_interface/p2p_2" BEL "wb_interface/p2p_1"
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BEL "wb_interface/p2p_0" BEL "wb_interface/rty" BEL "wb_interface/err"
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BEL "wb_interface/ack" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_5" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_6" BEL
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"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_7" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_5" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_6" BEL
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"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_7" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_5" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_6" BEL
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"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_7" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_7" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_6" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_5" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_4" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_3" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_2" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_1" BEL
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"datafifowrite/custom_fifo_dp5/fifo_out_0" BEL
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"datafifowrite/custom_fifo_dp5/addr_rd_0" BEL
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"datafifowrite/custom_fifo_dp5/addr_wr_0" BEL
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"datafifowrite/custom_fifo_dp5/addr_rd_2" BEL
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"datafifowrite/custom_fifo_dp5/addr_wr_2" BEL
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"datafifowrite/custom_fifo_dp5/addr_rd_1" BEL
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"datafifowrite/custom_fifo_dp5/addr_wr_1" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_5" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_6" BEL
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"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_7" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_5" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_6" BEL
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"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_7" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_5" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_6" BEL
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"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_7" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_7" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_6" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_5" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_4" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_3" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_2" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_1" BEL
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"datafifowrite/custom_fifo_dp6/fifo_out_0" BEL
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"datafifowrite/custom_fifo_dp6/addr_rd_0" BEL
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"datafifowrite/custom_fifo_dp6/addr_wr_0" BEL
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| 138 |
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"datafifowrite/custom_fifo_dp6/addr_rd_2" BEL
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| 139 |
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"datafifowrite/custom_fifo_dp6/addr_wr_2" BEL
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| 140 |
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"datafifowrite/custom_fifo_dp6/addr_rd_1" BEL
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| 141 |
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"datafifowrite/custom_fifo_dp6/addr_wr_1" BEL
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| 142 |
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_0" BEL
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_1" BEL
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_3" BEL
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_4" BEL
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_5" BEL
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| 148 |
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_6" BEL
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| 149 |
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"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_7" BEL
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| 150 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_0" BEL
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| 151 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_1" BEL
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| 152 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_2" BEL
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| 153 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_3" BEL
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| 154 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_4" BEL
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| 155 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_5" BEL
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| 156 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6" BEL
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| 157 |
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"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7" BEL
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| 158 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_0" BEL
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| 159 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_1" BEL
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| 160 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_2" BEL
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| 161 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_3" BEL
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| 162 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_4" BEL
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| 163 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_5" BEL
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| 164 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_6" BEL
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| 165 |
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"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_7" BEL
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| 166 |
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"datafifowrite/custom_fifo_dp7/fifo_out_7" BEL
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| 167 |
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"datafifowrite/custom_fifo_dp7/fifo_out_6" BEL
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| 168 |
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"datafifowrite/custom_fifo_dp7/fifo_out_5" BEL
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| 169 |
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"datafifowrite/custom_fifo_dp7/fifo_out_4" BEL
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| 170 |
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"datafifowrite/custom_fifo_dp7/fifo_out_3" BEL
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| 171 |
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"datafifowrite/custom_fifo_dp7/fifo_out_2" BEL
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| 172 |
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"datafifowrite/custom_fifo_dp7/fifo_out_1" BEL
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| 173 |
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"datafifowrite/custom_fifo_dp7/fifo_out_0" BEL
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| 174 |
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"datafifowrite/custom_fifo_dp7/addr_rd_0" BEL
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| 175 |
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"datafifowrite/custom_fifo_dp7/addr_wr_0" BEL
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| 176 |
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"datafifowrite/custom_fifo_dp7/addr_rd_2" BEL
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| 177 |
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"datafifowrite/custom_fifo_dp7/addr_wr_2" BEL
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| 178 |
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"datafifowrite/custom_fifo_dp7/addr_rd_1" BEL
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| 179 |
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"datafifowrite/custom_fifo_dp7/addr_wr_1" BEL
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| 180 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_0" BEL
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| 181 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_1" BEL
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| 182 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_2" BEL
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_3" BEL
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| 184 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_4" BEL
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| 185 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_5" BEL
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| 186 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_6" BEL
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| 187 |
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"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_7" BEL
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| 188 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_0" BEL
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| 189 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_1" BEL
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| 190 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_2" BEL
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| 191 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_3" BEL
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| 192 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_4" BEL
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| 193 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_5" BEL
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| 194 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_6" BEL
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| 195 |
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"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_7" BEL
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| 196 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_0" BEL
|
| 197 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_1" BEL
|
| 198 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_2" BEL
|
| 199 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_3" BEL
|
| 200 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_4" BEL
|
| 201 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_5" BEL
|
| 202 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_6" BEL
|
| 203 |
|
|
"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_7" BEL
|
| 204 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_7" BEL
|
| 205 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_6" BEL
|
| 206 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_5" BEL
|
| 207 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_4" BEL
|
| 208 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_3" BEL
|
| 209 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_2" BEL
|
| 210 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_1" BEL
|
| 211 |
|
|
"datafifowrite/custom_fifo_dp8/fifo_out_0" BEL
|
| 212 |
|
|
"datafifowrite/custom_fifo_dp8/addr_rd_0" BEL
|
| 213 |
|
|
"datafifowrite/custom_fifo_dp8/addr_wr_0" BEL
|
| 214 |
|
|
"datafifowrite/custom_fifo_dp8/addr_rd_2" BEL
|
| 215 |
|
|
"datafifowrite/custom_fifo_dp8/addr_wr_2" BEL
|
| 216 |
|
|
"datafifowrite/custom_fifo_dp8/addr_rd_1" BEL
|
| 217 |
|
|
"datafifowrite/custom_fifo_dp8/addr_wr_1" BEL "wb_interface/size_6"
|
| 218 |
|
|
BEL "wb_interface/size_5" BEL "wb_interface/size_4" BEL
|
| 219 |
|
|
"wb_interface/size_3" BEL "wb_interface/size_2" BEL
|
| 220 |
|
|
"wb_interface/size_1" BEL "wb_interface/size_0" BEL
|
| 221 |
|
|
"wb_clk_i_BUFGP/BUFG.GCLKMUX" BEL "wb_clk_i_BUFGP/BUFG";
|
| 222 |
|
|
TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
|
| 223 |
|
|
SCHEMATIC END;
|
| 224 |
|
|
|
