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jeaander |
Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.12 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.14 secs
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--> Reading design: wiegand_tx_top.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "wiegand_tx_top.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "wiegand_tx_top"
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Output Format : NGC
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Target Device : xc3s700an-4-fgg484
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---- Source Options
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Top Module Name : wiegand_tx_top
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 24
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling verilog file "../../../../../rtl/verilog/wb_interface.v" in library work
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Compiling verilog include file "../../../../../rtl/verilog/wiegand_defines.v"
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Compiling verilog file "../../../../../rtl/verilog/fifos.v" in library work
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Compiling verilog include file "../../../../../rtl/verilog/wiegand_defines.v"
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Module compiled
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Module compiled
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Module compiled
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Compiling verilog file "../../../../../rtl/verilog/wiegand_tx_top.v" in library work
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Compiling verilog include file "../../../../../rtl/verilog/wiegand_defines.v"
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Module compiled
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Module compiled
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No errors in compilation
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Analysis of file <"wiegand_tx_top.prj"> succeeded.
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=========================================================================
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* Design Hierarchy Analysis *
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=========================================================================
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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Analyzing hierarchy for module in library .
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=========================================================================
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* HDL Analysis *
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=========================================================================
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Analyzing top module .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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Analyzing module in library .
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Module is correct for synthesis.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Performing bidirectional port resolution...
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Synthesizing Unit .
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Related source file is "../../../../../rtl/verilog/wb_interface.v".
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WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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Found 32-bit register for signal .
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Found 32-bit tristate buffer for signal .
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Found 32-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 9-bit register for signal .
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Found 32-bit 4-to-1 multiplexer for signal .
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Summary:
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inferred 44 D-type flip-flop(s).
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inferred 32 Multiplexer(s).
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inferred 32 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "../../../../../rtl/verilog/fifos.v".
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Found 8-bit tristate buffer for signal .
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Found 8-bit register for signal .
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Summary:
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inferred 8 D-type flip-flop(s).
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inferred 8 Tristate(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "../../../../../rtl/verilog/fifos.v".
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Found 3-bit comparator equal for signal .
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Found 3-bit register for signal .
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Found 3-bit register for signal .
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Found 8-bit register for signal .
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Summary:
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inferred 14 D-type flip-flop(s).
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inferred 1 Comparator(s).
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "../../../../../rtl/verilog/fifos.v".
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Unit synthesized.
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Synthesizing Unit .
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Related source file is "../../../../../rtl/verilog/wiegand_tx_top.v".
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WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.
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Found finite state machine for signal .
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-----------------------------------------------------------------------
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| States | 6 |
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| Transitions | 12 |
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| Inputs | 5 |
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| Outputs | 5 |
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| Clock | clk (rising_edge) |
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| Reset | rst (positive) |
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| Reset type | asynchronous |
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| Reset State | 000 |
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| Encoding | automatic |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 7-bit up counter for signal .
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Found 7-bit up counter for signal .
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Found 1-bit register for signal .
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Found 1-bit register for signal .
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Found 5-bit up counter for signal .
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Found 32-bit up counter for signal .
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Found 32-bit comparator equal for signal created at line 192.
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Found 7-bit comparator equal for signal created at line 193.
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Found 32-bit comparator equal for signal created at line 202.
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Found 32-bit register for signal .
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Summary:
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inferred 1 Finite State Machine(s).
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inferred 4 Counter(s).
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inferred 36 D-type flip-flop(s).
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inferred 3 Comparator(s).
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Unit synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Counters : 4
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32-bit up counter : 1
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5-bit up counter : 1
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7-bit up counter : 2
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# Registers : 51
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1-bit register : 31
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32-bit register : 3
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8-bit register : 16
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9-bit register : 1
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# Comparators : 7
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3-bit comparator equal : 4
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32-bit comparator equal : 2
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7-bit comparator equal : 1
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# Multiplexers : 1
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32-bit 4-to-1 multiplexer : 1
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# Tristates : 13
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32-bit tristate buffer : 1
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8-bit tristate buffer : 12
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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Analyzing FSM for best encoding.
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Optimizing FSM on signal with gray encoding.
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-------------------
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State | Encoding
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-------------------
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000 | 000
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001 | 001
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100 | 010
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101 | 011
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110 | 111
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111 | 110
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-------------------
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# FSMs : 1
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# Counters : 4
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32-bit up counter : 1
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5-bit up counter : 1
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7-bit up counter : 2
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# Registers : 264
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Flip-Flops : 264
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# Comparators : 7
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3-bit comparator equal : 4
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32-bit comparator equal : 2
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7-bit comparator equal : 1
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# Multiplexers : 1
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32-bit 4-to-1 multiplexer : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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WARNING:Xst:2042 - Unit mem_byte: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
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Optimizing unit ...
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Optimizing unit ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block wiegand_tx_top, actual ratio is 3.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Macro Statistics
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# Registers : 318
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Flip-Flops : 318
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Final Report *
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=========================================================================
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Final Results
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RTL Top Level Output File Name : wiegand_tx_top.ngr
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Top Level Output File Name : wiegand_tx_top
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Output Format : NGC
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Optimization Goal : Speed
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Keep Hierarchy : No
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Design Statistics
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# IOs : 87
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Cell Usage :
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# BELS : 414
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# GND : 1
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# INV : 1
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# LUT2 : 7
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# LUT2_D : 2
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# LUT2_L : 1
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# LUT3 : 39
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# LUT3_D : 3
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# LUT3_L : 1
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# LUT4 : 245
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# LUT4_L : 6
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# MUXCY : 63
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# MUXF5 : 12
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# VCC : 1
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# XORCY : 32
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# FlipFlops/Latches : 318
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# FDC : 76
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# FDC_1 : 3
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# FDCE : 158
|
| 374 |
|
|
# FDCE_1 : 69
|
| 375 |
|
|
# FDPE : 8
|
| 376 |
|
|
# FDPE_1 : 4
|
| 377 |
|
|
# Clock Buffers : 1
|
| 378 |
|
|
# BUFGP : 1
|
| 379 |
|
|
# IO Buffers : 79
|
| 380 |
|
|
# IBUF : 42
|
| 381 |
|
|
# OBUF : 5
|
| 382 |
|
|
# OBUFT : 32
|
| 383 |
|
|
=========================================================================
|
| 384 |
|
|
|
| 385 |
|
|
Device utilization summary:
|
| 386 |
|
|
---------------------------
|
| 387 |
|
|
|
| 388 |
|
|
Selected Device : 3s700anfgg484-4
|
| 389 |
|
|
|
| 390 |
|
|
Number of Slices: 243 out of 5888 4%
|
| 391 |
|
|
Number of Slice Flip Flops: 318 out of 11776 2%
|
| 392 |
|
|
Number of 4 input LUTs: 305 out of 11776 2%
|
| 393 |
|
|
Number of IOs: 87
|
| 394 |
|
|
Number of bonded IOBs: 80 out of 372 21%
|
| 395 |
|
|
Number of GCLKs: 1 out of 24 4%
|
| 396 |
|
|
|
| 397 |
|
|
---------------------------
|
| 398 |
|
|
Partition Resource Summary:
|
| 399 |
|
|
---------------------------
|
| 400 |
|
|
|
| 401 |
|
|
No Partitions were found in this design.
|
| 402 |
|
|
|
| 403 |
|
|
---------------------------
|
| 404 |
|
|
|
| 405 |
|
|
|
| 406 |
|
|
=========================================================================
|
| 407 |
|
|
TIMING REPORT
|
| 408 |
|
|
|
| 409 |
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
| 410 |
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
| 411 |
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
| 412 |
|
|
|
| 413 |
|
|
Clock Information:
|
| 414 |
|
|
------------------
|
| 415 |
|
|
-----------------------------------+------------------------+-------+
|
| 416 |
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
| 417 |
|
|
-----------------------------------+------------------------+-------+
|
| 418 |
|
|
wb_clk_i | BUFGP | 318 |
|
| 419 |
|
|
-----------------------------------+------------------------+-------+
|
| 420 |
|
|
|
| 421 |
|
|
Asynchronous Control Signals Information:
|
| 422 |
|
|
----------------------------------------
|
| 423 |
|
|
-----------------------------------+----------------------------------------------+-------+
|
| 424 |
|
|
Control Signal | Buffer(FF name) | Load |
|
| 425 |
|
|
-----------------------------------+----------------------------------------------+-------+
|
| 426 |
|
|
wb_rst_i | IBUF | 166 |
|
| 427 |
|
|
_or0000(_or00001:O) | NONE(datafifowrite/custom_fifo_dp5/addr_rd_0)| 152 |
|
| 428 |
|
|
-----------------------------------+----------------------------------------------+-------+
|
| 429 |
|
|
|
| 430 |
|
|
Timing Summary:
|
| 431 |
|
|
---------------
|
| 432 |
|
|
Speed Grade: -4
|
| 433 |
|
|
|
| 434 |
|
|
Minimum period: 12.521ns (Maximum Frequency: 79.865MHz)
|
| 435 |
|
|
Minimum input arrival time before clock: 7.398ns
|
| 436 |
|
|
Maximum output required time after clock: 7.061ns
|
| 437 |
|
|
Maximum combinational path delay: 9.636ns
|
| 438 |
|
|
|
| 439 |
|
|
Timing Detail:
|
| 440 |
|
|
--------------
|
| 441 |
|
|
All values displayed in nanoseconds (ns)
|
| 442 |
|
|
|
| 443 |
|
|
=========================================================================
|
| 444 |
|
|
Timing constraint: Default period analysis for Clock 'wb_clk_i'
|
| 445 |
|
|
Clock period: 12.521ns (frequency: 79.865MHz)
|
| 446 |
|
|
Total number of paths / destination ports: 3668 / 390
|
| 447 |
|
|
-------------------------------------------------------------------------
|
| 448 |
|
|
Delay: 6.261ns (Levels of Logic = 33)
|
| 449 |
|
|
Source: state_FSM_FFd1 (FF)
|
| 450 |
|
|
Destination: pulseCnt_31 (FF)
|
| 451 |
|
|
Source Clock: wb_clk_i rising
|
| 452 |
|
|
Destination Clock: wb_clk_i falling
|
| 453 |
|
|
|
| 454 |
|
|
Data Path: state_FSM_FFd1 to pulseCnt_31
|
| 455 |
|
|
Gate Net
|
| 456 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 457 |
|
|
---------------------------------------- ------------
|
| 458 |
|
|
FDC:C->Q 52 0.591 1.349 state_FSM_FFd1 (state_FSM_FFd1)
|
| 459 |
|
|
LUT4:I1->O 1 0.643 0.000 Mcount_pulseCnt_lut<0> (Mcount_pulseCnt_lut<0>)
|
| 460 |
|
|
MUXCY:S->O 1 0.632 0.000 Mcount_pulseCnt_cy<0> (Mcount_pulseCnt_cy<0>)
|
| 461 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<1> (Mcount_pulseCnt_cy<1>)
|
| 462 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<2> (Mcount_pulseCnt_cy<2>)
|
| 463 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<3> (Mcount_pulseCnt_cy<3>)
|
| 464 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<4> (Mcount_pulseCnt_cy<4>)
|
| 465 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<5> (Mcount_pulseCnt_cy<5>)
|
| 466 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<6> (Mcount_pulseCnt_cy<6>)
|
| 467 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<7> (Mcount_pulseCnt_cy<7>)
|
| 468 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<8> (Mcount_pulseCnt_cy<8>)
|
| 469 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<9> (Mcount_pulseCnt_cy<9>)
|
| 470 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<10> (Mcount_pulseCnt_cy<10>)
|
| 471 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<11> (Mcount_pulseCnt_cy<11>)
|
| 472 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<12> (Mcount_pulseCnt_cy<12>)
|
| 473 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<13> (Mcount_pulseCnt_cy<13>)
|
| 474 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<14> (Mcount_pulseCnt_cy<14>)
|
| 475 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<15> (Mcount_pulseCnt_cy<15>)
|
| 476 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<16> (Mcount_pulseCnt_cy<16>)
|
| 477 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<17> (Mcount_pulseCnt_cy<17>)
|
| 478 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<18> (Mcount_pulseCnt_cy<18>)
|
| 479 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<19> (Mcount_pulseCnt_cy<19>)
|
| 480 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<20> (Mcount_pulseCnt_cy<20>)
|
| 481 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<21> (Mcount_pulseCnt_cy<21>)
|
| 482 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<22> (Mcount_pulseCnt_cy<22>)
|
| 483 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<23> (Mcount_pulseCnt_cy<23>)
|
| 484 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<24> (Mcount_pulseCnt_cy<24>)
|
| 485 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<25> (Mcount_pulseCnt_cy<25>)
|
| 486 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<26> (Mcount_pulseCnt_cy<26>)
|
| 487 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<27> (Mcount_pulseCnt_cy<27>)
|
| 488 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<28> (Mcount_pulseCnt_cy<28>)
|
| 489 |
|
|
MUXCY:CI->O 1 0.065 0.000 Mcount_pulseCnt_cy<29> (Mcount_pulseCnt_cy<29>)
|
| 490 |
|
|
MUXCY:CI->O 0 0.065 0.000 Mcount_pulseCnt_cy<30> (Mcount_pulseCnt_cy<30>)
|
| 491 |
|
|
XORCY:CI->O 1 0.844 0.000 Mcount_pulseCnt_xor<31> (Mcount_pulseCnt31)
|
| 492 |
|
|
FDC:D 0.252 pulseCnt_31
|
| 493 |
|
|
----------------------------------------
|
| 494 |
|
|
Total 6.261ns (4.912ns logic, 1.349ns route)
|
| 495 |
|
|
(78.5% logic, 21.5% route)
|
| 496 |
|
|
|
| 497 |
|
|
=========================================================================
|
| 498 |
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'wb_clk_i'
|
| 499 |
|
|
Total number of paths / destination ports: 959 / 255
|
| 500 |
|
|
-------------------------------------------------------------------------
|
| 501 |
|
|
Offset: 7.398ns (Levels of Logic = 5)
|
| 502 |
|
|
Source: wb_adr_i<4> (PAD)
|
| 503 |
|
|
Destination: wb_interface/pulsewidth_0 (FF)
|
| 504 |
|
|
Destination Clock: wb_clk_i falling
|
| 505 |
|
|
|
| 506 |
|
|
Data Path: wb_adr_i<4> to wb_interface/pulsewidth_0
|
| 507 |
|
|
Gate Net
|
| 508 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 509 |
|
|
---------------------------------------- ------------
|
| 510 |
|
|
IBUF:I->O 2 0.849 0.590 wb_adr_i_4_IBUF (wb_adr_i_4_IBUF)
|
| 511 |
|
|
LUT3:I0->O 1 0.648 0.500 _and000011_SW0 (N115)
|
| 512 |
|
|
LUT4:I1->O 4 0.643 0.590 _and000011 (N34)
|
| 513 |
|
|
LUT4:I3->O 5 0.648 0.713 _and000012 (N32)
|
| 514 |
|
|
LUT2:I1->O 32 0.643 1.262 wb_interface/pulsewidth_and00001 (wb_interface/pulsewidth_and0000)
|
| 515 |
|
|
FDCE_1:CE 0.312 wb_interface/pulsewidth_0
|
| 516 |
|
|
----------------------------------------
|
| 517 |
|
|
Total 7.398ns (3.743ns logic, 3.655ns route)
|
| 518 |
|
|
(50.6% logic, 49.4% route)
|
| 519 |
|
|
|
| 520 |
|
|
=========================================================================
|
| 521 |
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'wb_clk_i'
|
| 522 |
|
|
Total number of paths / destination ports: 96 / 37
|
| 523 |
|
|
-------------------------------------------------------------------------
|
| 524 |
|
|
Offset: 7.061ns (Levels of Logic = 3)
|
| 525 |
|
|
Source: wb_interface/p2p_8 (FF)
|
| 526 |
|
|
Destination: wb_dat_o<8> (PAD)
|
| 527 |
|
|
Source Clock: wb_clk_i falling
|
| 528 |
|
|
|
| 529 |
|
|
Data Path: wb_interface/p2p_8 to wb_dat_o<8>
|
| 530 |
|
|
Gate Net
|
| 531 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 532 |
|
|
---------------------------------------- ------------
|
| 533 |
|
|
FDCE_1:C->Q 3 0.591 0.611 wb_interface/p2p_8 (wb_interface/p2p_8)
|
| 534 |
|
|
LUT4:I1->O 1 0.643 0.000 wb_interface/Mmux_wb_dat_rdbk401 (wb_interface/Mmux_wb_dat_rdbk40)
|
| 535 |
|
|
MUXF5:I1->O 1 0.276 0.420 wb_interface/Mmux_wb_dat_rdbk40_f5 (wb_interface/wb_dat_rdbk<8>)
|
| 536 |
|
|
OBUFT:I->O 4.520 wb_dat_o_8_OBUFT (wb_dat_o<8>)
|
| 537 |
|
|
----------------------------------------
|
| 538 |
|
|
Total 7.061ns (6.030ns logic, 1.031ns route)
|
| 539 |
|
|
(85.4% logic, 14.6% route)
|
| 540 |
|
|
|
| 541 |
|
|
=========================================================================
|
| 542 |
|
|
Timing constraint: Default path analysis
|
| 543 |
|
|
Total number of paths / destination ports: 342 / 32
|
| 544 |
|
|
-------------------------------------------------------------------------
|
| 545 |
|
|
Delay: 9.636ns (Levels of Logic = 6)
|
| 546 |
|
|
Source: wb_adr_i<1> (PAD)
|
| 547 |
|
|
Destination: wb_dat_o<8> (PAD)
|
| 548 |
|
|
|
| 549 |
|
|
Data Path: wb_adr_i<1> to wb_dat_o<8>
|
| 550 |
|
|
Gate Net
|
| 551 |
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
| 552 |
|
|
---------------------------------------- ------------
|
| 553 |
|
|
IBUF:I->O 2 0.849 0.590 wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)
|
| 554 |
|
|
LUT4:I0->O 1 0.648 0.000 wb_interface/Mmux_wb_dat_rdbk1411 (wb_interface/Mmux_wb_dat_rdbk1411)
|
| 555 |
|
|
MUXF5:I0->O 43 0.276 1.409 wb_interface/Mmux_wb_dat_rdbk141_f5 (N01)
|
| 556 |
|
|
LUT4:I0->O 1 0.648 0.000 wb_interface/Mmux_wb_dat_rdbk401 (wb_interface/Mmux_wb_dat_rdbk40)
|
| 557 |
|
|
MUXF5:I1->O 1 0.276 0.420 wb_interface/Mmux_wb_dat_rdbk40_f5 (wb_interface/wb_dat_rdbk<8>)
|
| 558 |
|
|
OBUFT:I->O 4.520 wb_dat_o_8_OBUFT (wb_dat_o<8>)
|
| 559 |
|
|
----------------------------------------
|
| 560 |
|
|
Total 9.636ns (7.217ns logic, 2.419ns route)
|
| 561 |
|
|
(74.9% logic, 25.1% route)
|
| 562 |
|
|
|
| 563 |
|
|
=========================================================================
|
| 564 |
|
|
|
| 565 |
|
|
|
| 566 |
|
|
Total REAL time to Xst completion: 7.00 secs
|
| 567 |
|
|
Total CPU time to Xst completion: 7.14 secs
|
| 568 |
|
|
|
| 569 |
|
|
-->
|
| 570 |
|
|
|
| 571 |
|
|
Total memory usage is 287180 kilobytes
|
| 572 |
|
|
|
| 573 |
|
|
Number of errors : 0 ( 0 filtered)
|
| 574 |
|
|
Number of warnings : 5 ( 0 filtered)
|
| 575 |
|
|
Number of infos : 0 ( 0 filtered)
|
| 576 |
|
|
|
