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[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [ise/] [wiegand_tx_top/] [wiegand_tx_top.twr] - Blame information for rev 17

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Line No. Rev Author Line
1 17 jeaander 
--------------------------------------------------------------------------------
2 
Release 14.7 Trace  (nt64)
3 
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
4 
 
5 
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
6 
-n 3 -fastpaths -xml wiegand_tx_top.twx wiegand_tx_top.ncd -o
7 
wiegand_tx_top.twr wiegand_tx_top.pcf -ucf wiegand_tx_top.ucf
8 
 
9 
Design file:              wiegand_tx_top.ncd
10 
Physical constraint file: wiegand_tx_top.pcf
11 
Device,package,speed:     xc3s700an,fgg484,-4 (PRODUCTION 1.42 2013-10-13)
12 
Report level:             verbose report
13 
 
14 
Environment Variable      Effect
15 
--------------------      ------
16 
NONE                      No environment variables were set
17 
--------------------------------------------------------------------------------
18 
 
19 
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
20 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
21 
   option. All paths that are not constrained will be reported in the
22 
   unconstrained paths section(s) of the report.
23 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
24 
   a 50 Ohm transmission line loading model.  For the details of this model,
25 
   and for more information on accounting for different loading conditions,
26 
   please see the device datasheet.
27 
INFO:Timing:3390 - This architecture does not support a default System Jitter
28 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
29 
   Uncertainty calculation.
30 
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
31 
   'Phase Error' calculations, these terms will be zero in the Clock
32 
   Uncertainty calculation.  Please make appropriate modification to
33 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
34 
   Error.
35 
 
36 
================================================================================
37 
Timing constraint: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
38 
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
39 
 
40 
 3668 paths analyzed, 850 endpoints analyzed, 0 failing endpoints
41 
 
42 
 Minimum period is  16.516ns.
43 
--------------------------------------------------------------------------------
44 
 
45 
Paths for end point state_FSM_FFd3 (SLICE_X10Y64.F4), 47 paths
46 
--------------------------------------------------------------------------------
47 
Slack (setup path):     1.742ns (requirement - (data path - clock path skew + uncertainty))
48 
  Source:               wb_interface/p2p_1 (FF)
49 
  Destination:          state_FSM_FFd3 (FF)
50 
  Requirement:          10.000ns
51 
  Data Path Delay:      8.106ns (Levels of Logic = 10)
52 
  Clock Path Skew:      -0.152ns (0.403 - 0.555)
53 
  Source Clock:         wb_clk_i_BUFGP falling at 10.000ns
54 
  Destination Clock:    wb_clk_i_BUFGP rising at 20.000ns
55 
  Clock Uncertainty:    0.000ns
56 
 
57 
  Maximum Data Path: wb_interface/p2p_1 to state_FSM_FFd3
58 
    Location             Delay type         Delay(ns)  Physical Resource
59 
                                                       Logical Resource(s)
60 
    -------------------------------------------------  -------------------
61 
    SLICE_X3Y80.XQ       Tcko                  0.591   wb_interface/p2p<1>
62 
                                                       wb_interface/p2p_1
63 
    SLICE_X3Y48.F3       net (fanout=3)        1.940   wb_interface/p2p<1>
64 
    SLICE_X3Y48.COUT     Topcyf                1.195   Mcompar_state_cmp_eq0001_cy<1>
65 
                                                       Mcompar_state_cmp_eq0001_lut<0>
66 
                                                       Mcompar_state_cmp_eq0001_cy<0>
67 
                                                       Mcompar_state_cmp_eq0001_cy<1>
68 
    SLICE_X3Y49.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<1>
69 
    SLICE_X3Y49.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<3>
70 
                                                       Mcompar_state_cmp_eq0001_cy<2>
71 
                                                       Mcompar_state_cmp_eq0001_cy<3>
72 
    SLICE_X3Y50.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<3>
73 
    SLICE_X3Y50.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<5>
74 
                                                       Mcompar_state_cmp_eq0001_cy<4>
75 
                                                       Mcompar_state_cmp_eq0001_cy<5>
76 
    SLICE_X3Y51.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<5>
77 
    SLICE_X3Y51.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<7>
78 
                                                       Mcompar_state_cmp_eq0001_cy<6>
79 
                                                       Mcompar_state_cmp_eq0001_cy<7>
80 
    SLICE_X3Y52.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<7>
81 
    SLICE_X3Y52.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<9>
82 
                                                       Mcompar_state_cmp_eq0001_cy<8>
83 
                                                       Mcompar_state_cmp_eq0001_cy<9>
84 
    SLICE_X3Y53.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<9>
85 
    SLICE_X3Y53.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<11>
86 
                                                       Mcompar_state_cmp_eq0001_cy<10>
87 
                                                       Mcompar_state_cmp_eq0001_cy<11>
88 
    SLICE_X3Y54.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<11>
89 
    SLICE_X3Y54.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<13>
90 
                                                       Mcompar_state_cmp_eq0001_cy<12>
91 
                                                       Mcompar_state_cmp_eq0001_cy<13>
92 
    SLICE_X3Y55.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<13>
93 
    SLICE_X3Y55.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<15>
94 
                                                       Mcompar_state_cmp_eq0001_cy<14>
95 
                                                       Mcompar_state_cmp_eq0001_cy<15>
96 
    SLICE_X10Y64.G4      net (fanout=2)        1.901   Mcompar_state_cmp_eq0001_cy<15>
97 
    SLICE_X10Y64.Y       Tilo                  0.707   state_FSM_FFd3
98 
                                                       state_FSM_FFd3-In74
99 
    SLICE_X10Y64.F4      net (fanout=1)        0.060   state_FSM_FFd3-In74/O
100 
    SLICE_X10Y64.CLK     Tfck                  0.802   state_FSM_FFd3
101 
                                                       state_FSM_FFd3-In87
102 
                                                       state_FSM_FFd3
103 
    -------------------------------------------------  ---------------------------
104 
    Total                                      8.106ns (4.205ns logic, 3.901ns route)
105 
                                                       (51.9% logic, 48.1% route)
106 
 
107 
--------------------------------------------------------------------------------
108 
Slack (setup path):     1.845ns (requirement - (data path - clock path skew + uncertainty))
109 
  Source:               wb_interface/p2p_3 (FF)
110 
  Destination:          state_FSM_FFd3 (FF)
111 
  Requirement:          10.000ns
112 
  Data Path Delay:      7.986ns (Levels of Logic = 10)
113 
  Clock Path Skew:      -0.169ns (0.403 - 0.572)
114 
  Source Clock:         wb_clk_i_BUFGP falling at 10.000ns
115 
  Destination Clock:    wb_clk_i_BUFGP rising at 20.000ns
116 
  Clock Uncertainty:    0.000ns
117 
 
118 
  Maximum Data Path: wb_interface/p2p_3 to state_FSM_FFd3
119 
    Location             Delay type         Delay(ns)  Physical Resource
120 
                                                       Logical Resource(s)
121 
    -------------------------------------------------  -------------------
122 
    SLICE_X2Y75.XQ       Tcko                  0.631   wb_interface/p2p<3>
123 
                                                       wb_interface/p2p_3
124 
    SLICE_X3Y48.G4       net (fanout=3)        1.797   wb_interface/p2p<3>
125 
    SLICE_X3Y48.COUT     Topcyg                1.178   Mcompar_state_cmp_eq0001_cy<1>
126 
                                                       Mcompar_state_cmp_eq0001_lut<1>
127 
                                                       Mcompar_state_cmp_eq0001_cy<1>
128 
    SLICE_X3Y49.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<1>
129 
    SLICE_X3Y49.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<3>
130 
                                                       Mcompar_state_cmp_eq0001_cy<2>
131 
                                                       Mcompar_state_cmp_eq0001_cy<3>
132 
    SLICE_X3Y50.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<3>
133 
    SLICE_X3Y50.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<5>
134 
                                                       Mcompar_state_cmp_eq0001_cy<4>
135 
                                                       Mcompar_state_cmp_eq0001_cy<5>
136 
    SLICE_X3Y51.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<5>
137 
    SLICE_X3Y51.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<7>
138 
                                                       Mcompar_state_cmp_eq0001_cy<6>
139 
                                                       Mcompar_state_cmp_eq0001_cy<7>
140 
    SLICE_X3Y52.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<7>
141 
    SLICE_X3Y52.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<9>
142 
                                                       Mcompar_state_cmp_eq0001_cy<8>
143 
                                                       Mcompar_state_cmp_eq0001_cy<9>
144 
    SLICE_X3Y53.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<9>
145 
    SLICE_X3Y53.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<11>
146 
                                                       Mcompar_state_cmp_eq0001_cy<10>
147 
                                                       Mcompar_state_cmp_eq0001_cy<11>
148 
    SLICE_X3Y54.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<11>
149 
    SLICE_X3Y54.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<13>
150 
                                                       Mcompar_state_cmp_eq0001_cy<12>
151 
                                                       Mcompar_state_cmp_eq0001_cy<13>
152 
    SLICE_X3Y55.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<13>
153 
    SLICE_X3Y55.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<15>
154 
                                                       Mcompar_state_cmp_eq0001_cy<14>
155 
                                                       Mcompar_state_cmp_eq0001_cy<15>
156 
    SLICE_X10Y64.G4      net (fanout=2)        1.901   Mcompar_state_cmp_eq0001_cy<15>
157 
    SLICE_X10Y64.Y       Tilo                  0.707   state_FSM_FFd3
158 
                                                       state_FSM_FFd3-In74
159 
    SLICE_X10Y64.F4      net (fanout=1)        0.060   state_FSM_FFd3-In74/O
160 
    SLICE_X10Y64.CLK     Tfck                  0.802   state_FSM_FFd3
161 
                                                       state_FSM_FFd3-In87
162 
                                                       state_FSM_FFd3
163 
    -------------------------------------------------  ---------------------------
164 
    Total                                      7.986ns (4.228ns logic, 3.758ns route)
165 
                                                       (52.9% logic, 47.1% route)
166 
 
167 
--------------------------------------------------------------------------------
168 
Slack (setup path):     1.918ns (requirement - (data path - clock path skew + uncertainty))
169 
  Source:               wb_interface/p2p_5 (FF)
170 
  Destination:          state_FSM_FFd3 (FF)
171 
  Requirement:          10.000ns
172 
  Data Path Delay:      7.917ns (Levels of Logic = 9)
173 
  Clock Path Skew:      -0.165ns (0.403 - 0.568)
174 
  Source Clock:         wb_clk_i_BUFGP falling at 10.000ns
175 
  Destination Clock:    wb_clk_i_BUFGP rising at 20.000ns
176 
  Clock Uncertainty:    0.000ns
177 
 
178 
  Maximum Data Path: wb_interface/p2p_5 to state_FSM_FFd3
179 
    Location             Delay type         Delay(ns)  Physical Resource
180 
                                                       Logical Resource(s)
181 
    -------------------------------------------------  -------------------
182 
    SLICE_X3Y76.XQ       Tcko                  0.591   wb_interface/p2p<5>
183 
                                                       wb_interface/p2p_5
184 
    SLICE_X3Y49.F1       net (fanout=3)        1.881   wb_interface/p2p<5>
185 
    SLICE_X3Y49.COUT     Topcyf                1.195   Mcompar_state_cmp_eq0001_cy<3>
186 
                                                       Mcompar_state_cmp_eq0001_lut<2>
187 
                                                       Mcompar_state_cmp_eq0001_cy<2>
188 
                                                       Mcompar_state_cmp_eq0001_cy<3>
189 
    SLICE_X3Y50.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<3>
190 
    SLICE_X3Y50.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<5>
191 
                                                       Mcompar_state_cmp_eq0001_cy<4>
192 
                                                       Mcompar_state_cmp_eq0001_cy<5>
193 
    SLICE_X3Y51.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<5>
194 
    SLICE_X3Y51.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<7>
195 
                                                       Mcompar_state_cmp_eq0001_cy<6>
196 
                                                       Mcompar_state_cmp_eq0001_cy<7>
197 
    SLICE_X3Y52.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<7>
198 
    SLICE_X3Y52.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<9>
199 
                                                       Mcompar_state_cmp_eq0001_cy<8>
200 
                                                       Mcompar_state_cmp_eq0001_cy<9>
201 
    SLICE_X3Y53.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<9>
202 
    SLICE_X3Y53.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<11>
203 
                                                       Mcompar_state_cmp_eq0001_cy<10>
204 
                                                       Mcompar_state_cmp_eq0001_cy<11>
205 
    SLICE_X3Y54.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<11>
206 
    SLICE_X3Y54.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<13>
207 
                                                       Mcompar_state_cmp_eq0001_cy<12>
208 
                                                       Mcompar_state_cmp_eq0001_cy<13>
209 
    SLICE_X3Y55.CIN      net (fanout=1)        0.000   Mcompar_state_cmp_eq0001_cy<13>
210 
    SLICE_X3Y55.COUT     Tbyp                  0.130   Mcompar_state_cmp_eq0001_cy<15>
211 
                                                       Mcompar_state_cmp_eq0001_cy<14>
212 
                                                       Mcompar_state_cmp_eq0001_cy<15>
213 
    SLICE_X10Y64.G4      net (fanout=2)        1.901   Mcompar_state_cmp_eq0001_cy<15>
214 
    SLICE_X10Y64.Y       Tilo                  0.707   state_FSM_FFd3
215 
                                                       state_FSM_FFd3-In74
216 
    SLICE_X10Y64.F4      net (fanout=1)        0.060   state_FSM_FFd3-In74/O
217 
    SLICE_X10Y64.CLK     Tfck                  0.802   state_FSM_FFd3
218 
                                                       state_FSM_FFd3-In87
219 
                                                       state_FSM_FFd3
220 
    -------------------------------------------------  ---------------------------
221 
    Total                                      7.917ns (4.075ns logic, 3.842ns route)
222 
                                                       (51.5% logic, 48.5% route)
223 
 
224 
--------------------------------------------------------------------------------
225 
 
226 
Paths for end point datafifowrite/custom_fifo_dp6/addr_rd_1 (SLICE_X11Y0.CE), 8 paths
227 
--------------------------------------------------------------------------------
228 
Slack (setup path):     2.087ns (requirement - (data path - clock path skew + uncertainty))
229 
  Source:               state_FSM_FFd2 (FF)
230 
  Destination:          datafifowrite/custom_fifo_dp6/addr_rd_1 (FF)
231 
  Requirement:          10.000ns
232 
  Data Path Delay:      7.836ns (Levels of Logic = 2)
233 
  Clock Path Skew:      -0.077ns (0.561 - 0.638)
234 
  Source Clock:         wb_clk_i_BUFGP rising at 0.000ns
235 
  Destination Clock:    wb_clk_i_BUFGP falling at 10.000ns
236 
  Clock Uncertainty:    0.000ns
237 
 
238 
  Maximum Data Path: state_FSM_FFd2 to datafifowrite/custom_fifo_dp6/addr_rd_1
239 
    Location             Delay type         Delay(ns)  Physical Resource
240 
                                                       Logical Resource(s)
241 
    -------------------------------------------------  -------------------
242 
    SLICE_X10Y65.XQ      Tcko                  0.631   state_FSM_FFd2
243 
                                                       state_FSM_FFd2
244 
    SLICE_X6Y51.G3       net (fanout=87)       2.122   state_FSM_FFd2
245 
    SLICE_X6Y51.Y        Tilo                  0.707   datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
246 
                                                       word_out_mux0000<10>11
247 
    SLICE_X11Y1.F2       net (fanout=8)        2.479   N4
248 
    SLICE_X11Y1.X        Tilo                  0.643   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
249 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
250 
    SLICE_X11Y0.CE       net (fanout=2)        0.943   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
251 
    SLICE_X11Y0.CLK      Tceck                 0.311   datafifowrite/custom_fifo_dp6/addr_rd<1>
252 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_1
253 
    -------------------------------------------------  ---------------------------
254 
    Total                                      7.836ns (2.292ns logic, 5.544ns route)
255 
                                                       (29.2% logic, 70.8% route)
256 
 
257 
--------------------------------------------------------------------------------
258 
Slack (setup path):     2.517ns (requirement - (data path - clock path skew + uncertainty))
259 
  Source:               state_FSM_FFd3 (FF)
260 
  Destination:          datafifowrite/custom_fifo_dp6/addr_rd_1 (FF)
261 
  Requirement:          10.000ns
262 
  Data Path Delay:      7.406ns (Levels of Logic = 2)
263 
  Clock Path Skew:      -0.077ns (0.561 - 0.638)
264 
  Source Clock:         wb_clk_i_BUFGP rising at 0.000ns
265 
  Destination Clock:    wb_clk_i_BUFGP falling at 10.000ns
266 
  Clock Uncertainty:    0.000ns
267 
 
268 
  Maximum Data Path: state_FSM_FFd3 to datafifowrite/custom_fifo_dp6/addr_rd_1
269 
    Location             Delay type         Delay(ns)  Physical Resource
270 
                                                       Logical Resource(s)
271 
    -------------------------------------------------  -------------------
272 
    SLICE_X10Y64.XQ      Tcko                  0.631   state_FSM_FFd3
273 
                                                       state_FSM_FFd3
274 
    SLICE_X6Y51.G2       net (fanout=86)       1.692   state_FSM_FFd3
275 
    SLICE_X6Y51.Y        Tilo                  0.707   datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
276 
                                                       word_out_mux0000<10>11
277 
    SLICE_X11Y1.F2       net (fanout=8)        2.479   N4
278 
    SLICE_X11Y1.X        Tilo                  0.643   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
279 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
280 
    SLICE_X11Y0.CE       net (fanout=2)        0.943   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
281 
    SLICE_X11Y0.CLK      Tceck                 0.311   datafifowrite/custom_fifo_dp6/addr_rd<1>
282 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_1
283 
    -------------------------------------------------  ---------------------------
284 
    Total                                      7.406ns (2.292ns logic, 5.114ns route)
285 
                                                       (30.9% logic, 69.1% route)
286 
 
287 
--------------------------------------------------------------------------------
288 
Slack (setup path):     15.134ns (requirement - (data path - clock path skew + uncertainty))
289 
  Source:               datafifowrite/custom_fifo_dp6/addr_wr_1 (FF)
290 
  Destination:          datafifowrite/custom_fifo_dp6/addr_rd_1 (FF)
291 
  Requirement:          20.000ns
292 
  Data Path Delay:      4.820ns (Levels of Logic = 2)
293 
  Clock Path Skew:      -0.046ns (0.212 - 0.258)
294 
  Source Clock:         wb_clk_i_BUFGP falling at 10.000ns
295 
  Destination Clock:    wb_clk_i_BUFGP falling at 30.000ns
296 
  Clock Uncertainty:    0.000ns
297 
 
298 
  Maximum Data Path: datafifowrite/custom_fifo_dp6/addr_wr_1 to datafifowrite/custom_fifo_dp6/addr_rd_1
299 
    Location             Delay type         Delay(ns)  Physical Resource
300 
                                                       Logical Resource(s)
301 
    -------------------------------------------------  -------------------
302 
    SLICE_X7Y4.XQ        Tcko                  0.591   datafifowrite/custom_fifo_dp6/addr_wr<1>
303 
                                                       datafifowrite/custom_fifo_dp6/addr_wr_1
304 
    SLICE_X9Y0.F2        net (fanout=8)        1.221   datafifowrite/custom_fifo_dp6/addr_wr<1>
305 
    SLICE_X9Y0.X         Tilo                  0.643   N125
306 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000_SW0
307 
    SLICE_X11Y1.F1       net (fanout=1)        0.468   N125
308 
    SLICE_X11Y1.X        Tilo                  0.643   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
309 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
310 
    SLICE_X11Y0.CE       net (fanout=2)        0.943   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
311 
    SLICE_X11Y0.CLK      Tceck                 0.311   datafifowrite/custom_fifo_dp6/addr_rd<1>
312 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_1
313 
    -------------------------------------------------  ---------------------------
314 
    Total                                      4.820ns (2.188ns logic, 2.632ns route)
315 
                                                       (45.4% logic, 54.6% route)
316 
 
317 
--------------------------------------------------------------------------------
318 
 
319 
Paths for end point datafifowrite/custom_fifo_dp6/addr_rd_0 (SLICE_X11Y0.CE), 8 paths
320 
--------------------------------------------------------------------------------
321 
Slack (setup path):     2.087ns (requirement - (data path - clock path skew + uncertainty))
322 
  Source:               state_FSM_FFd2 (FF)
323 
  Destination:          datafifowrite/custom_fifo_dp6/addr_rd_0 (FF)
324 
  Requirement:          10.000ns
325 
  Data Path Delay:      7.836ns (Levels of Logic = 2)
326 
  Clock Path Skew:      -0.077ns (0.561 - 0.638)
327 
  Source Clock:         wb_clk_i_BUFGP rising at 0.000ns
328 
  Destination Clock:    wb_clk_i_BUFGP falling at 10.000ns
329 
  Clock Uncertainty:    0.000ns
330 
 
331 
  Maximum Data Path: state_FSM_FFd2 to datafifowrite/custom_fifo_dp6/addr_rd_0
332 
    Location             Delay type         Delay(ns)  Physical Resource
333 
                                                       Logical Resource(s)
334 
    -------------------------------------------------  -------------------
335 
    SLICE_X10Y65.XQ      Tcko                  0.631   state_FSM_FFd2
336 
                                                       state_FSM_FFd2
337 
    SLICE_X6Y51.G3       net (fanout=87)       2.122   state_FSM_FFd2
338 
    SLICE_X6Y51.Y        Tilo                  0.707   datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
339 
                                                       word_out_mux0000<10>11
340 
    SLICE_X11Y1.F2       net (fanout=8)        2.479   N4
341 
    SLICE_X11Y1.X        Tilo                  0.643   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
342 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
343 
    SLICE_X11Y0.CE       net (fanout=2)        0.943   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
344 
    SLICE_X11Y0.CLK      Tceck                 0.311   datafifowrite/custom_fifo_dp6/addr_rd<1>
345 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_0
346 
    -------------------------------------------------  ---------------------------
347 
    Total                                      7.836ns (2.292ns logic, 5.544ns route)
348 
                                                       (29.2% logic, 70.8% route)
349 
 
350 
--------------------------------------------------------------------------------
351 
Slack (setup path):     2.517ns (requirement - (data path - clock path skew + uncertainty))
352 
  Source:               state_FSM_FFd3 (FF)
353 
  Destination:          datafifowrite/custom_fifo_dp6/addr_rd_0 (FF)
354 
  Requirement:          10.000ns
355 
  Data Path Delay:      7.406ns (Levels of Logic = 2)
356 
  Clock Path Skew:      -0.077ns (0.561 - 0.638)
357 
  Source Clock:         wb_clk_i_BUFGP rising at 0.000ns
358 
  Destination Clock:    wb_clk_i_BUFGP falling at 10.000ns
359 
  Clock Uncertainty:    0.000ns
360 
 
361 
  Maximum Data Path: state_FSM_FFd3 to datafifowrite/custom_fifo_dp6/addr_rd_0
362 
    Location             Delay type         Delay(ns)  Physical Resource
363 
                                                       Logical Resource(s)
364 
    -------------------------------------------------  -------------------
365 
    SLICE_X10Y64.XQ      Tcko                  0.631   state_FSM_FFd3
366 
                                                       state_FSM_FFd3
367 
    SLICE_X6Y51.G2       net (fanout=86)       1.692   state_FSM_FFd3
368 
    SLICE_X6Y51.Y        Tilo                  0.707   datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
369 
                                                       word_out_mux0000<10>11
370 
    SLICE_X11Y1.F2       net (fanout=8)        2.479   N4
371 
    SLICE_X11Y1.X        Tilo                  0.643   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
372 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
373 
    SLICE_X11Y0.CE       net (fanout=2)        0.943   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
374 
    SLICE_X11Y0.CLK      Tceck                 0.311   datafifowrite/custom_fifo_dp6/addr_rd<1>
375 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_0
376 
    -------------------------------------------------  ---------------------------
377 
    Total                                      7.406ns (2.292ns logic, 5.114ns route)
378 
                                                       (30.9% logic, 69.1% route)
379 
 
380 
--------------------------------------------------------------------------------
381 
Slack (setup path):     15.134ns (requirement - (data path - clock path skew + uncertainty))
382 
  Source:               datafifowrite/custom_fifo_dp6/addr_wr_1 (FF)
383 
  Destination:          datafifowrite/custom_fifo_dp6/addr_rd_0 (FF)
384 
  Requirement:          20.000ns
385 
  Data Path Delay:      4.820ns (Levels of Logic = 2)
386 
  Clock Path Skew:      -0.046ns (0.212 - 0.258)
387 
  Source Clock:         wb_clk_i_BUFGP falling at 10.000ns
388 
  Destination Clock:    wb_clk_i_BUFGP falling at 30.000ns
389 
  Clock Uncertainty:    0.000ns
390 
 
391 
  Maximum Data Path: datafifowrite/custom_fifo_dp6/addr_wr_1 to datafifowrite/custom_fifo_dp6/addr_rd_0
392 
    Location             Delay type         Delay(ns)  Physical Resource
393 
                                                       Logical Resource(s)
394 
    -------------------------------------------------  -------------------
395 
    SLICE_X7Y4.XQ        Tcko                  0.591   datafifowrite/custom_fifo_dp6/addr_wr<1>
396 
                                                       datafifowrite/custom_fifo_dp6/addr_wr_1
397 
    SLICE_X9Y0.F2        net (fanout=8)        1.221   datafifowrite/custom_fifo_dp6/addr_wr<1>
398 
    SLICE_X9Y0.X         Tilo                  0.643   N125
399 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000_SW0
400 
    SLICE_X11Y1.F1       net (fanout=1)        0.468   N125
401 
    SLICE_X11Y1.X        Tilo                  0.643   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
402 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
403 
    SLICE_X11Y0.CE       net (fanout=2)        0.943   datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
404 
    SLICE_X11Y0.CLK      Tceck                 0.311   datafifowrite/custom_fifo_dp6/addr_rd<1>
405 
                                                       datafifowrite/custom_fifo_dp6/addr_rd_0
406 
    -------------------------------------------------  ---------------------------
407 
    Total                                      4.820ns (2.188ns logic, 2.632ns route)
408 
                                                       (45.4% logic, 54.6% route)
409 
 
410 
--------------------------------------------------------------------------------
411 
 
412 
Hold Paths: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
413 
--------------------------------------------------------------------------------
414 
 
415 
Paths for end point datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7 (SLICE_X2Y23.CE), 1 path
416 
--------------------------------------------------------------------------------
417 
Slack (hold path):      0.975ns (requirement - (clock path skew + uncertainty - data path))
418 
  Source:               datafifowrite/custom_fifo_dp7/addr_wr_1 (FF)
419 
  Destination:          datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7 (FF)
420 
  Requirement:          0.000ns
421 
  Data Path Delay:      1.147ns (Levels of Logic = 0)
422 
  Clock Path Skew:      0.172ns (0.626 - 0.454)
423 
  Source Clock:         wb_clk_i_BUFGP falling at 30.000ns
424 
  Destination Clock:    wb_clk_i_BUFGP falling at 30.000ns
425 
  Clock Uncertainty:    0.000ns
426 
 
427 
  Minimum Data Path: datafifowrite/custom_fifo_dp7/addr_wr_1 to datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7
428 
    Location             Delay type         Delay(ns)  Physical Resource
429 
                                                       Logical Resource(s)
430 
    -------------------------------------------------  -------------------
431 
    SLICE_X2Y26.XQ       Tcko                  0.505   datafifowrite/custom_fifo_dp7/addr_wr<1>
432 
                                                       datafifowrite/custom_fifo_dp7/addr_wr_1
433 
    SLICE_X2Y23.CE       net (fanout=8)        0.642   datafifowrite/custom_fifo_dp7/addr_wr<1>
434 
    SLICE_X2Y23.CLK      Tckce       (-Th)     0.000   datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg<7>
435 
                                                       datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7
436 
    -------------------------------------------------  ---------------------------
437 
    Total                                      1.147ns (0.505ns logic, 0.642ns route)
438 
                                                       (44.0% logic, 56.0% route)
439 
 
440 
--------------------------------------------------------------------------------
441 
 
442 
Paths for end point datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6 (SLICE_X2Y23.CE), 1 path
443 
--------------------------------------------------------------------------------
444 
Slack (hold path):      0.975ns (requirement - (clock path skew + uncertainty - data path))
445 
  Source:               datafifowrite/custom_fifo_dp7/addr_wr_1 (FF)
446 
  Destination:          datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6 (FF)
447 
  Requirement:          0.000ns
448 
  Data Path Delay:      1.147ns (Levels of Logic = 0)
449 
  Clock Path Skew:      0.172ns (0.626 - 0.454)
450 
  Source Clock:         wb_clk_i_BUFGP falling at 30.000ns
451 
  Destination Clock:    wb_clk_i_BUFGP falling at 30.000ns
452 
  Clock Uncertainty:    0.000ns
453 
 
454 
  Minimum Data Path: datafifowrite/custom_fifo_dp7/addr_wr_1 to datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6
455 
    Location             Delay type         Delay(ns)  Physical Resource
456 
                                                       Logical Resource(s)
457 
    -------------------------------------------------  -------------------
458 
    SLICE_X2Y26.XQ       Tcko                  0.505   datafifowrite/custom_fifo_dp7/addr_wr<1>
459 
                                                       datafifowrite/custom_fifo_dp7/addr_wr_1
460 
    SLICE_X2Y23.CE       net (fanout=8)        0.642   datafifowrite/custom_fifo_dp7/addr_wr<1>
461 
    SLICE_X2Y23.CLK      Tckce       (-Th)     0.000   datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg<7>
462 
                                                       datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6
463 
    -------------------------------------------------  ---------------------------
464 
    Total                                      1.147ns (0.505ns logic, 0.642ns route)
465 
                                                       (44.0% logic, 56.0% route)
466 
 
467 
--------------------------------------------------------------------------------
468 
 
469 
Paths for end point datafifowrite/custom_fifo_dp8/addr_wr_0 (SLICE_X0Y51.BY), 1 path
470 
--------------------------------------------------------------------------------
471 
Slack (hold path):      1.015ns (requirement - (clock path skew + uncertainty - data path))
472 
  Source:               datafifowrite/custom_fifo_dp8/addr_wr_2 (FF)
473 
  Destination:          datafifowrite/custom_fifo_dp8/addr_wr_0 (FF)
474 
  Requirement:          0.000ns
475 
  Data Path Delay:      1.031ns (Levels of Logic = 0)
476 
  Clock Path Skew:      0.016ns (0.110 - 0.094)
477 
  Source Clock:         wb_clk_i_BUFGP falling at 30.000ns
478 
  Destination Clock:    wb_clk_i_BUFGP falling at 30.000ns
479 
  Clock Uncertainty:    0.000ns
480 
 
481 
  Minimum Data Path: datafifowrite/custom_fifo_dp8/addr_wr_2 to datafifowrite/custom_fifo_dp8/addr_wr_0
482 
    Location             Delay type         Delay(ns)  Physical Resource
483 
                                                       Logical Resource(s)
484 
    -------------------------------------------------  -------------------
485 
    SLICE_X1Y50.YQ       Tcko                  0.464   datafifowrite/custom_fifo_dp8/addr_wr<2>
486 
                                                       datafifowrite/custom_fifo_dp8/addr_wr_2
487 
    SLICE_X0Y51.BY       net (fanout=8)        0.394   datafifowrite/custom_fifo_dp8/addr_wr<2>
488 
    SLICE_X0Y51.CLK      Tckdi       (-Th)    -0.173   datafifowrite/custom_fifo_dp8/addr_wr<1>
489 
                                                       datafifowrite/custom_fifo_dp8/addr_wr_0
490 
    -------------------------------------------------  ---------------------------
491 
    Total                                      1.031ns (0.637ns logic, 0.394ns route)
492 
                                                       (61.8% logic, 38.2% route)
493 
 
494 
--------------------------------------------------------------------------------
495 
 
496 
Component Switching Limit Checks: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
497 
--------------------------------------------------------------------------------
498 
Slack: 16.796ns (period - (min low pulse limit / (low pulse / period)))
499 
  Period: 20.000ns
500 
  Low pulse: 10.000ns
501 
  Low pulse limit: 1.602ns (Trpw)
502 
  Physical resource: state_FSM_FFd2/SR
503 
  Logical resource: state_FSM_FFd2/SR
504 
  Location pin: SLICE_X10Y65.SR
505 
  Clock network: wb_rst_i_IBUF
506 
--------------------------------------------------------------------------------
507 
Slack: 16.796ns (period - (min high pulse limit / (high pulse / period)))
508 
  Period: 20.000ns
509 
  High pulse: 10.000ns
510 
  High pulse limit: 1.602ns (Trpw)
511 
  Physical resource: state_FSM_FFd2/SR
512 
  Logical resource: state_FSM_FFd2/SR
513 
  Location pin: SLICE_X10Y65.SR
514 
  Clock network: wb_rst_i_IBUF
515 
--------------------------------------------------------------------------------
516 
Slack: 16.796ns (period - (min low pulse limit / (low pulse / period)))
517 
  Period: 20.000ns
518 
  Low pulse: 10.000ns
519 
  Low pulse limit: 1.602ns (Trpw)
520 
  Physical resource: wb_interface/ack/SR
521 
  Logical resource: wb_interface/ack/SR
522 
  Location pin: SLICE_X0Y76.SR
523 
  Clock network: wb_rst_i_IBUF
524 
--------------------------------------------------------------------------------
525 
 
526 
 
527 
All constraints were met.
528 
 
529 
 
530 
Data Sheet report:
531 
-----------------
532 
All values displayed in nanoseconds (ns)
533 
 
534 
Clock to Setup on destination clock wb_clk_i
535 
---------------+---------+---------+---------+---------+
536 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
537 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
538 
---------------+---------+---------+---------+---------+
539 
wb_clk_i       |    9.531|    8.258|    7.913|    8.557|
540 
---------------+---------+---------+---------+---------+
541 
 
542 
 
543 
Timing summary:
544 
---------------
545 
 
546 
Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)
547 
 
548 
Constraints cover 3668 paths, 0 nets, and 1308 connections
549 
 
550 
Design statistics:
551 
   Minimum period:  16.516ns{1}   (Maximum frequency:  60.547MHz)
552 
 
553 
 
554 
------------------------------------Footnotes-----------------------------------
555 
1)  The minimum period statistic assumes all single cycle delays.
556 
 
557 
Analysis completed Mon Feb 16 11:08:59 2015
558 
--------------------------------------------------------------------------------
559 
 
560 
Trace Settings:
561 
-------------------------
562 
Trace Settings
563 
 
564 
Peak Memory Usage: 195 MB
565 
 
566 
 
567 
 

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