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[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [vivado/] [wiegand_tx_top/] [wiegand_tx_top.runs/] [synth_1/] [wiegand_tx_top.tcl] - Blame information for rev 17

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Line No. Rev Author Line
1 17 jeaander
# 
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# Synthesis run script generated by Vivado
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# 
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  set_param gui.test TreeTableDev
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set_msg_config -id {HDL 9-1061} -limit 100000
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set_msg_config -id {HDL 9-1654} -limit 100000
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create_project -in_memory -part xc7vx485tffg1157-1
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set_property target_language Verilog [current_project]
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set_param project.compositeFile.enableAutoGeneration 0
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set_property default_lib xil_defaultlib [current_project]
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read_verilog C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v
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set_property file_type "Verilog Header" [get_files C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v]
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read_verilog -library xil_defaultlib {
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  C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v
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  C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v
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  C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v
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}
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read_xdc C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top/wiegand_tx_top.srcs/constrs_1/new/wiegand_tx_top.xdc
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set_property used_in_implementation false [get_files C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top/wiegand_tx_top.srcs/constrs_1/new/wiegand_tx_top.xdc]
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set_param synth.vivado.isSynthRun true
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set_property webtalk.parent_dir C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top/wiegand_tx_top.cache/wt [current_project]
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set_property parent.project_dir C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top [current_project]
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catch { write_hwdef -file wiegand_tx_top.hwdef }
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synth_design -top wiegand_tx_top -part xc7vx485tffg1157-1
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write_checkpoint wiegand_tx_top.dcp
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report_utilization -file wiegand_tx_top_utilization_synth.rpt -pb wiegand_tx_top_utilization_synth.pb

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