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jeaander |
#
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# Vivado (TM) v2014.2 (64-bit)
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#
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# .tcl: Tcl script for re-creating project 'wiegand_tx_top'
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#
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# Generated by Vivado on Mon Feb 16 11:27:17 -0500 2015
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# IP Build 924643 on Fri May 30 09:20:16 MDT 2014
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#
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# This file contains the Vivado Tcl commands for re-creating the project to the state*
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# when this script was generated. In order to re-create the project, please source this
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# file in the Vivado Tcl Shell.
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#
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# * Note that the runs in the created project will be configured the same way as the
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# original project, however they will not be launched automatically. To regenerate the
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# run results please launch the synthesis/implementation runs as needed.
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#
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#*****************************************************************************************
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# NOTE: In order to use this script for source control purposes, please make sure that the
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# following files are added to the source control system:-
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#
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# 1. This project restoration tcl script (.tcl) that was generated.
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#
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# 2. The following source(s) files that were local or imported into the original project.
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# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
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#
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# <none>
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#
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# 3. The following remote source files that were added to the original project:-
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#
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# "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v"
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# "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v"
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# "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v"
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# "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v"
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# "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top/wiegand_tx_top.srcs/constrs_1/new/wiegand_tx_top.xdc"
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#
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#*****************************************************************************************
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir "."
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# Set the directory path for the original project from where this script was exported
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set orig_proj_dir "[file normalize "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top"]"
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# Create project
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create_project wiegand_tx_top ./wiegand_tx_top
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# Set the directory path for the new project
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set proj_dir [get_property directory [current_project]]
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# Set project properties
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set obj [get_projects wiegand_tx_top]
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set_property "board_part" "" $obj
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set_property "compxlib.compiled_library_dir" "$proj_dir/wiegand_tx_top.cache/compile_simlib" $obj
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set_property "compxlib.edk.exclude_sub_libs" "0" $obj
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set_property "compxlib.edk.exclude_superseded_cores" "1" $obj
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set_property "compxlib.edk.previous_lib_path" "" $obj
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set_property "compxlib.edk.source_lib" "" $obj
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set_property "compxlib.edklib" "0" $obj
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set_property "compxlib.funcsim" "1" $obj
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set_property "compxlib.overwrite_libs" "0" $obj
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set_property "compxlib.timesim" "1" $obj
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set_property "compxlib.xilinxcorelib" "1" $obj
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set_property "default_lib" "xil_defaultlib" $obj
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set_property "managed_ip" "0" $obj
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set_property "part" "xc7vx485tffg1157-1" $obj
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set_property "simulator_language" "Mixed" $obj
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set_property "source_mgmt_mode" "All" $obj
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set_property "target_language" "Verilog" $obj
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set_property "target_simulator" "XSim" $obj
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# Create 'sources_1' fileset (if not found)
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if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
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}
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# Set 'sources_1' fileset object
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set obj [get_filesets sources_1]
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set files [list \
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"[file normalize "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v"]"\
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"[file normalize "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v"]"\
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"[file normalize "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v"]"\
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"[file normalize "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v"]"\
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]
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add_files -norecurse -fileset $obj $files
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# Set 'sources_1' fileset file properties for remote files
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set file "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property "file_type" "Verilog Header" $file_obj
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set_property "is_enabled" "1" $file_obj
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set_property "is_global_include" "0" $file_obj
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set_property "library" "xil_defaultlib" $file_obj
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set_property "path_mode" "RelativeFirst" $file_obj
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set_property "used_in" "synthesis simulation" $file_obj
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set_property "used_in_simulation" "1" $file_obj
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set_property "used_in_synthesis" "1" $file_obj
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set file "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property "file_type" "Verilog" $file_obj
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set_property "is_enabled" "1" $file_obj
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set_property "is_global_include" "0" $file_obj
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set_property "library" "xil_defaultlib" $file_obj
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set_property "path_mode" "RelativeFirst" $file_obj
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set_property "used_in" "synthesis implementation simulation" $file_obj
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set_property "used_in_implementation" "1" $file_obj
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set_property "used_in_simulation" "1" $file_obj
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set_property "used_in_synthesis" "1" $file_obj
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set file "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property "file_type" "Verilog" $file_obj
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set_property "is_enabled" "1" $file_obj
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set_property "is_global_include" "0" $file_obj
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set_property "library" "xil_defaultlib" $file_obj
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set_property "path_mode" "RelativeFirst" $file_obj
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set_property "used_in" "synthesis implementation simulation" $file_obj
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set_property "used_in_implementation" "1" $file_obj
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set_property "used_in_simulation" "1" $file_obj
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set_property "used_in_synthesis" "1" $file_obj
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set file "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
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set_property "file_type" "Verilog" $file_obj
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set_property "is_enabled" "1" $file_obj
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set_property "is_global_include" "0" $file_obj
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set_property "library" "xil_defaultlib" $file_obj
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set_property "path_mode" "RelativeFirst" $file_obj
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set_property "used_in" "synthesis implementation simulation" $file_obj
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set_property "used_in_implementation" "1" $file_obj
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set_property "used_in_simulation" "1" $file_obj
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set_property "used_in_synthesis" "1" $file_obj
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# Set 'sources_1' fileset file properties for local files
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# None
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# Set 'sources_1' fileset properties
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set obj [get_filesets sources_1]
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set_property "design_mode" "RTL" $obj
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set_property "edif_extra_search_paths" "" $obj
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set_property "generic" "" $obj
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set_property "include_dirs" "" $obj
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set_property "lib_map_file" "" $obj
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| 149 |
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set_property "loop_count" "1000" $obj
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| 150 |
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set_property "name" "sources_1" $obj
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set_property "top" "wiegand_tx_top" $obj
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set_property "verilog_define" "" $obj
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set_property "verilog_uppercase" "0" $obj
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| 154 |
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| 155 |
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# Create 'constrs_1' fileset (if not found)
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if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
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}
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# Set 'constrs_1' fileset object
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set obj [get_filesets constrs_1]
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# Add/Import constrs file and set constrs file properties
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set file "[file normalize "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top/wiegand_tx_top.srcs/constrs_1/new/wiegand_tx_top.xdc"]"
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set file_added [add_files -norecurse -fileset $obj $file]
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| 166 |
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set file "$origin_dir/../../../../Desktop/rtl/wiegand/trunk/syn/xilinx/wiegand_tx/vivado/wiegand_tx_top/wiegand_tx_top.srcs/constrs_1/new/wiegand_tx_top.xdc"
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set file [file normalize $file]
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set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property "file_type" "XDC" $file_obj
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| 170 |
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set_property "is_enabled" "1" $file_obj
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| 171 |
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set_property "is_global_include" "0" $file_obj
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| 172 |
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set_property "library" "xil_defaultlib" $file_obj
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| 173 |
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set_property "path_mode" "RelativeFirst" $file_obj
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| 174 |
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set_property "processing_order" "NORMAL" $file_obj
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| 175 |
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set_property "scoped_to_cells" "" $file_obj
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| 176 |
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set_property "scoped_to_ref" "" $file_obj
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| 177 |
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set_property "used_in" "synthesis implementation" $file_obj
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| 178 |
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set_property "used_in_implementation" "1" $file_obj
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| 179 |
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set_property "used_in_synthesis" "1" $file_obj
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| 180 |
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| 181 |
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# Set 'constrs_1' fileset properties
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set obj [get_filesets constrs_1]
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set_property "name" "constrs_1" $obj
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| 184 |
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set_property "target_constrs_file" "" $obj
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| 185 |
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| 186 |
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# Create 'sim_1' fileset (if not found)
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| 187 |
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if {[string equal [get_filesets -quiet sim_1] ""]} {
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| 188 |
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create_fileset -simset sim_1
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| 189 |
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}
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| 190 |
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| 191 |
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# Set 'sim_1' fileset object
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set obj [get_filesets sim_1]
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# Empty (no sources present)
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# Set 'sim_1' fileset properties
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set obj [get_filesets sim_1]
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set_property "generic" "" $obj
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| 198 |
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set_property "include_dirs" "" $obj
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| 199 |
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set_property "name" "sim_1" $obj
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| 200 |
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set_property "nl.cell" "" $obj
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| 201 |
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set_property "nl.incl_unisim_models" "0" $obj
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| 202 |
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set_property "nl.process_corner" "slow" $obj
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| 203 |
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set_property "nl.rename_top" "" $obj
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| 204 |
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set_property "nl.sdf_anno" "1" $obj
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| 205 |
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set_property "nl.write_all_overrides" "0" $obj
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| 206 |
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set_property "runtime" "1000ns" $obj
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| 207 |
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set_property "source_set" "sources_1" $obj
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| 208 |
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set_property "top" "wiegand_tx_top" $obj
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| 209 |
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set_property "unit_under_test" "" $obj
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| 210 |
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set_property "verilog_define" "" $obj
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| 211 |
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set_property "verilog_uppercase" "0" $obj
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| 212 |
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set_property "xelab.debug_level" "typical" $obj
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| 213 |
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set_property "xelab.dll" "0" $obj
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| 214 |
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set_property "xelab.load_glbl" "1" $obj
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| 215 |
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set_property "xelab.more_options" "" $obj
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| 216 |
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set_property "xelab.mt_level" "auto" $obj
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| 217 |
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set_property "xelab.nosort" "0" $obj
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| 218 |
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set_property "xelab.rangecheck" "0" $obj
|
| 219 |
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set_property "xelab.relax" "1" $obj
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| 220 |
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set_property "xelab.sdf_delay" "sdfmax" $obj
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| 221 |
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set_property "xelab.snapshot" "" $obj
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| 222 |
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set_property "xelab.unifast" "0" $obj
|
| 223 |
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set_property "xsim.more_options" "" $obj
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| 224 |
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set_property "xsim.saif" "" $obj
|
| 225 |
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set_property "xsim.tclbatch" "" $obj
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| 226 |
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set_property "xsim.view" "" $obj
|
| 227 |
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set_property "xsim.wdb" "" $obj
|
| 228 |
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|
| 229 |
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# Create 'synth_1' run (if not found)
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| 230 |
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if {[string equal [get_runs -quiet synth_1] ""]} {
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| 231 |
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create_run -name synth_1 -part xc7vx485tffg1157-1 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
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| 232 |
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} else {
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| 233 |
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set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
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| 234 |
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set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
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| 235 |
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}
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| 236 |
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set obj [get_runs synth_1]
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| 237 |
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set_property "constrset" "constrs_1" $obj
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| 238 |
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set_property "description" "Vivado Synthesis Defaults" $obj
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| 239 |
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set_property "flow" "Vivado Synthesis 2014" $obj
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| 240 |
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set_property "name" "synth_1" $obj
|
| 241 |
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set_property "needs_refresh" "0" $obj
|
| 242 |
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set_property "part" "xc7vx485tffg1157-1" $obj
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| 243 |
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set_property "srcset" "sources_1" $obj
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| 244 |
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set_property "strategy" "Vivado Synthesis Defaults" $obj
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| 245 |
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set_property "incremental_checkpoint" "" $obj
|
| 246 |
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set_property "steps.synth_design.tcl.pre" "" $obj
|
| 247 |
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set_property "steps.synth_design.tcl.post" "" $obj
|
| 248 |
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set_property "steps.synth_design.args.flatten_hierarchy" "rebuilt" $obj
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| 249 |
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set_property "steps.synth_design.args.gated_clock_conversion" "off" $obj
|
| 250 |
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set_property "steps.synth_design.args.bufg" "12" $obj
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| 251 |
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set_property "steps.synth_design.args.fanout_limit" "10000" $obj
|
| 252 |
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set_property "steps.synth_design.args.directive" "Default" $obj
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| 253 |
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set_property "steps.synth_design.args.fsm_extraction" "auto" $obj
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| 254 |
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set_property "steps.synth_design.args.keep_equivalent_registers" "0" $obj
|
| 255 |
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set_property "steps.synth_design.args.resource_sharing" "auto" $obj
|
| 256 |
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set_property "steps.synth_design.args.control_set_opt_threshold" "4" $obj
|
| 257 |
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set_property "steps.synth_design.args.no_lc" "0" $obj
|
| 258 |
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set_property "steps.synth_design.args.shreg_min_size" "3" $obj
|
| 259 |
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set_property "steps.synth_design.args.max_bram" "-1" $obj
|
| 260 |
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set_property "steps.synth_design.args.max_dsp" "-1" $obj
|
| 261 |
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set_property -name {steps.synth_design.args.more options} -value {} -objects $obj
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| 262 |
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|
| 263 |
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|
# set the current synth run
|
| 264 |
|
|
current_run -synthesis [get_runs synth_1]
|
| 265 |
|
|
|
| 266 |
|
|
# Create 'impl_1' run (if not found)
|
| 267 |
|
|
if {[string equal [get_runs -quiet impl_1] ""]} {
|
| 268 |
|
|
create_run -name impl_1 -part xc7vx485tffg1157-1 -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
|
| 269 |
|
|
} else {
|
| 270 |
|
|
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
| 271 |
|
|
set_property flow "Vivado Implementation 2014" [get_runs impl_1]
|
| 272 |
|
|
}
|
| 273 |
|
|
set obj [get_runs impl_1]
|
| 274 |
|
|
set_property "constrset" "constrs_1" $obj
|
| 275 |
|
|
set_property "description" "Vivado Implementation Defaults" $obj
|
| 276 |
|
|
set_property "flow" "Vivado Implementation 2014" $obj
|
| 277 |
|
|
set_property "name" "impl_1" $obj
|
| 278 |
|
|
set_property "needs_refresh" "0" $obj
|
| 279 |
|
|
set_property "part" "xc7vx485tffg1157-1" $obj
|
| 280 |
|
|
set_property "srcset" "sources_1" $obj
|
| 281 |
|
|
set_property "strategy" "Vivado Implementation Defaults" $obj
|
| 282 |
|
|
set_property "incremental_checkpoint" "" $obj
|
| 283 |
|
|
set_property "steps.opt_design.is_enabled" "1" $obj
|
| 284 |
|
|
set_property "steps.opt_design.tcl.pre" "" $obj
|
| 285 |
|
|
set_property "steps.opt_design.tcl.post" "" $obj
|
| 286 |
|
|
set_property "steps.opt_design.args.verbose" "0" $obj
|
| 287 |
|
|
set_property "steps.opt_design.args.directive" "Default" $obj
|
| 288 |
|
|
set_property -name {steps.opt_design.args.more options} -value {} -objects $obj
|
| 289 |
|
|
set_property "steps.power_opt_design.is_enabled" "0" $obj
|
| 290 |
|
|
set_property "steps.power_opt_design.tcl.pre" "" $obj
|
| 291 |
|
|
set_property "steps.power_opt_design.tcl.post" "" $obj
|
| 292 |
|
|
set_property -name {steps.power_opt_design.args.more options} -value {} -objects $obj
|
| 293 |
|
|
set_property "steps.place_design.tcl.pre" "" $obj
|
| 294 |
|
|
set_property "steps.place_design.tcl.post" "" $obj
|
| 295 |
|
|
set_property "steps.place_design.args.directive" "Default" $obj
|
| 296 |
|
|
set_property -name {steps.place_design.args.more options} -value {} -objects $obj
|
| 297 |
|
|
set_property "steps.post_place_power_opt_design.is_enabled" "0" $obj
|
| 298 |
|
|
set_property "steps.post_place_power_opt_design.tcl.pre" "" $obj
|
| 299 |
|
|
set_property "steps.post_place_power_opt_design.tcl.post" "" $obj
|
| 300 |
|
|
set_property -name {steps.post_place_power_opt_design.args.more options} -value {} -objects $obj
|
| 301 |
|
|
set_property "steps.phys_opt_design.is_enabled" "0" $obj
|
| 302 |
|
|
set_property "steps.phys_opt_design.tcl.pre" "" $obj
|
| 303 |
|
|
set_property "steps.phys_opt_design.tcl.post" "" $obj
|
| 304 |
|
|
set_property "steps.phys_opt_design.args.directive" "Default" $obj
|
| 305 |
|
|
set_property -name {steps.phys_opt_design.args.more options} -value {} -objects $obj
|
| 306 |
|
|
set_property "steps.route_design.tcl.pre" "" $obj
|
| 307 |
|
|
set_property "steps.route_design.tcl.post" "" $obj
|
| 308 |
|
|
set_property "steps.route_design.args.directive" "Default" $obj
|
| 309 |
|
|
set_property -name {steps.route_design.args.more options} -value {} -objects $obj
|
| 310 |
|
|
set_property "steps.post_route_phys_opt_design.is_enabled" "0" $obj
|
| 311 |
|
|
set_property "steps.post_route_phys_opt_design.tcl.pre" "" $obj
|
| 312 |
|
|
set_property "steps.post_route_phys_opt_design.tcl.post" "" $obj
|
| 313 |
|
|
set_property "steps.post_route_phys_opt_design.args.directive" "Default" $obj
|
| 314 |
|
|
set_property -name {steps.post_route_phys_opt_design.args.more options} -value {} -objects $obj
|
| 315 |
|
|
set_property "steps.write_bitstream.tcl.pre" "" $obj
|
| 316 |
|
|
set_property "steps.write_bitstream.tcl.post" "" $obj
|
| 317 |
|
|
set_property "steps.write_bitstream.args.raw_bitfile" "0" $obj
|
| 318 |
|
|
set_property "steps.write_bitstream.args.mask_file" "0" $obj
|
| 319 |
|
|
set_property "steps.write_bitstream.args.no_binary_bitfile" "0" $obj
|
| 320 |
|
|
set_property "steps.write_bitstream.args.bin_file" "0" $obj
|
| 321 |
|
|
set_property "steps.write_bitstream.args.logic_location_file" "0" $obj
|
| 322 |
|
|
set_property -name {steps.write_bitstream.args.more options} -value {} -objects $obj
|
| 323 |
|
|
|
| 324 |
|
|
# set the current impl run
|
| 325 |
|
|
current_run -implementation [get_runs impl_1]
|
| 326 |
|
|
|
| 327 |
|
|
puts "INFO: Project created:wiegand_tx_top"
|
