OpenCores
URL https://opencores.org/ocsvn/xenie/xenie/trunk

Subversion Repositories xenie

[/] [xenie/] [trunk/] [examples/] [Eth_example/] [mb_fw/] [drivers/] [iic_v3_4/] [src/] [xiic_selftest.c] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 DFC
/******************************************************************************
2
*
3
* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
4
*
5
* Permission is hereby granted, free of charge, to any person obtaining a copy
6
* of this software and associated documentation files (the "Software"), to deal
7
* in the Software without restriction, including without limitation the rights
8
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9
* copies of the Software, and to permit persons to whom the Software is
10
* furnished to do so, subject to the following conditions:
11
*
12
* The above copyright notice and this permission notice shall be included in
13
* all copies or substantial portions of the Software.
14
*
15
* Use of the Software is limited solely to applications:
16
* (a) running on a Xilinx device, or
17
* (b) that interact with a Xilinx device through a bus or interconnect.
18
*
19
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
23
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
24
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25
* SOFTWARE.
26
*
27
* Except as contained in this notice, the name of the Xilinx shall not be used
28
* in advertising or otherwise to promote the sale, use or other dealings in
29
* this Software without prior written authorization from Xilinx.
30
*
31
******************************************************************************/
32
/*****************************************************************************/
33
/**
34
*
35
* @file xiic_selftest.c
36
* @addtogroup iic_v3_1
37
* @{
38
*
39
* Contains selftest functions for the XIic component.
40
*
41
* <pre>
42
* MODIFICATION HISTORY:
43
*
44
* Ver   Who  Date     Changes
45
* ----- --- ------- -----------------------------------------------
46
* 1.01b jhl 03/26/02 repartioned the driver
47
* 1.01c ecm 12/05/02 new rev
48
* 1.01c sv  05/09/05 Changed the data being written to the Address/Control
49
*                    Register and removed the code for testing the
50
*                    Receive Data Register.
51
* 1.13a wgr 03/22/07 Converted to new coding style.
52
* 1.16a ktn 07/17/09 Updated the test to test only Interrupt Registers
53
*                    as the software reset only resets the interrupt logic
54
*                    and the Interrupt Registers are set to default values.
55
* 1.16a ktn 10/16/09 Updated the notes in the XIic_SelfTest() API and
56
*                    XIIC_RESET macro to mention that the complete IIC core
57
*                    is Reset on giving a software reset to the IIC core.
58
*                    Some previous versions of the core only reset the
59
*                    Interrupt Logic/Registers, please refer to the HW
60
*                    specification for futher details.
61
* 2.00a ktn 10/22/09 Converted all register accesses to 32 bit access.
62
*                    Updated to use the HAL APIs/macros.
63
*                    Some of the macros have been renamed to remove _m from
64
*                    the name and some of the macros have been renamed to be
65
*                    consistent, see the xiic_i.h and xiic_l.h files for further
66
*                    information
67
* </pre>
68
*
69
****************************************************************************/
70
 
71
/***************************** Include Files *******************************/
72
 
73
#include "xiic.h"
74
#include "xiic_i.h"
75
 
76
/************************** Constant Definitions ***************************/
77
 
78
 
79
/**************************** Type Definitions *****************************/
80
 
81
 
82
/***************** Macros (Inline Functions) Definitions *******************/
83
 
84
 
85
/************************** Function Prototypes ****************************/
86
 
87
 
88
/************************** Variable Definitions **************************/
89
 
90
 
91
/*****************************************************************************/
92
/**
93
*
94
* Runs a limited self-test on the driver/device. This test does a read/write
95
* test of the Interrupt Registers There is no loopback capabilities for the
96
* device such that this test does not send or receive data.
97
*
98
* @param        InstancePtr is a pointer to the XIic instance to be worked on.
99
*
100
* @return
101
*               - XST_SUCCESS if no errors are found
102
*               - XST_FAILURE if errors are found
103
*
104
* @note         None.
105
*
106
****************************************************************************/
107
int XIic_SelfTest(XIic *InstancePtr)
108
{
109
        int Status = XST_SUCCESS;
110
        int GlobalIntrStatus;
111
        u32 IntrEnableStatus;
112
 
113
        Xil_AssertNonvoid(InstancePtr != NULL);
114
        Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
115
 
116
        /*
117
         * Store the Global Interrupt Register and the Interrupt Enable Register
118
         * contents.
119
         */
120
        GlobalIntrStatus = XIic_IsIntrGlobalEnabled(InstancePtr->BaseAddress);
121
        IntrEnableStatus = XIic_ReadIier(InstancePtr->BaseAddress);
122
 
123
        /*
124
         * Reset the device so it's in a known state and the default state of
125
         * the interrupt registers can be tested.
126
         */
127
        XIic_Reset(InstancePtr);
128
 
129
        if (XIic_IsIntrGlobalEnabled(InstancePtr->BaseAddress)!= 0) {
130
                Status = XST_FAILURE;
131
        }
132
 
133
        if (XIic_ReadIier(InstancePtr->BaseAddress)!= 0) {
134
                Status = XST_FAILURE;
135
        }
136
 
137
        /*
138
         * Test Read/Write to the Interrupt Enable register.
139
         */
140
        XIic_WriteIier(InstancePtr->BaseAddress, XIIC_TX_RX_INTERRUPTS);
141
        if (XIic_ReadIier(InstancePtr->BaseAddress)!= XIIC_TX_RX_INTERRUPTS) {
142
                Status = XST_FAILURE;
143
        }
144
 
145
        /*
146
         * Reset device to remove the affects of the previous test.
147
         */
148
        XIic_Reset(InstancePtr);
149
 
150
        /*
151
         * Restore the Global Interrupt Register and the Interrupt Enable
152
         * Register contents.
153
         */
154
        if (GlobalIntrStatus == TRUE) {
155
                XIic_IntrGlobalEnable(InstancePtr->BaseAddress);
156
        }
157
        XIic_WriteIier(InstancePtr->BaseAddress, IntrEnableStatus);
158
 
159
        return Status;
160
}
161
/** @} */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.