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-------------------------------------------------------------------------------

-- Title      : RXAUI Core Level Clocking

-- Project    : RXAUI

-------------------------------------------------------------------------------

-- File       : rxaui_0_cl_clocking.vhd

-------------------------------------------------------------------------------

-- Description: This module holds the per-core clocking for the

--              RXAUI core

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-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;

entity rxaui_0_cl_clocking is

    port (

      txoutclk             : in  std_logic;

      clk156               : out std_logic

      );

end rxaui_0_cl_clocking;

architecture rtl of rxaui_0_cl_clocking is

  signal clkfbout          : std_logic;

begin

  clk156_bufg_i : BUFG

    port map (

      I => txoutclk,

      O => clk156);

end rtl;