OpenCores
URL https://opencores.org/ocsvn/xge_ll_mac/xge_ll_mac/trunk

Subversion Repositories xge_ll_mac

[/] [xge_ll_mac/] [trunk/] [rtl/] [oc_mac.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 cleberCAG
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  This file is part of the "10GE LL MAC" project              ////
4
////  http://www.opencores.org/cores/xge_ll_mac/                  ////
5
////                                                              ////
6
////  This project is derived from the "10GE MAC" project of      ////
7
////  A. Tanguay (antanguay@opencores.org) by Andreas Peters      ////
8
////  for his Diploma Thesis at the University of Heidelberg.     ////
9
////  The Thesis was supervised by Christian Leber                ////
10
////                                                              ////
11
////  Author(s):                                                  ////
12
////      - Andreas Peters                                        ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2008-2012 AUTHORS. All rights reserved.        ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
 
41
//`include "technology.h"
42
`include "oc_mac.h"
43
`default_nettype none
44
module oc_mac (
45
                input wire              res_n,
46
                input wire              clk,
47
                input wire              tx_start,
48
                input wire [63:0]        tx_data,
49
                input wire [7:0] tx_data_valid,
50
                input wire [63:0]        xgmii_rxd,
51
                input wire [7:0] xgmii_rxc,
52
 
53
                output wire             tx_ack,
54
                output wire             rx_bad_frame,
55
                output wire             rx_good_frame,
56
                output wire [63:0]       rx_data,
57
                output wire [7:0]        rx_data_valid,
58
                output wire [7:0]        xgmii_txc,
59
                output wire[63:0]        xgmii_txd
60
        );
61
 
62
wire [1:0]       local_fault_msg_det;
63
wire [1:0]       remote_fault_msg_det;
64
wire            status_fragment_error_tog;
65
wire            status_pause_frame_rx_tog;
66
 
67
 
68
wire [63:0]      txdfifo_wdata;
69
wire [7:0]       txdfifo_wstatus;
70
 
71
wire [63:0]      xgmii_data_in;
72
wire [7:0]       xgmii_data_status;
73
 
74
 
75
rx_enqueue rx_eq0(
76
                  // Outputs
77
                .xgmii_data_in          (xgmii_data_in),
78
                .xgmii_data_status      (xgmii_data_status),
79
                .local_fault_msg_det  (local_fault_msg_det),
80
                .remote_fault_msg_det (remote_fault_msg_det),
81
                .status_fragment_error_tog(status_fragment_error_tog),
82
                .status_pause_frame_rx_tog(status_pause_frame_rx_tog),
83
                // Inputs
84
                .clk                    (clk),
85
                .res_n                  (res_n),
86
                .xgmii_rxd              (xgmii_rxd),
87
                .xgmii_rxc              (xgmii_rxc));
88
 
89
 
90
rx_control rx_ctrl(
91
                  // Outputs
92
                .rx_data                (rx_data),
93
                .rx_data_valid          (rx_data_valid),
94
                .rx_good_frame          (rx_good_frame),
95
                .rx_bad_frame           (rx_bad_frame),
96
                //.status_rxdfifo_udflow_tog(status_rxdfifo_udflow_tog),
97
                // Inputs
98
                .clk                    (clk),
99
                .res_n                  (res_n),
100
                .rx_inc_data            (xgmii_data_in),
101
                .rx_inc_status          (xgmii_data_status));
102
 
103
 
104
tx_dequeue tx_dq0(
105
                  // Outputs
106
                .xgmii_txd              (xgmii_txd),
107
                .xgmii_txc              (xgmii_txc),
108
                // Inputs
109
                .clk                    (clk),
110
                .res_n                  (res_n),
111
                .txdfifo_rdata          (txdfifo_wdata),
112
                .txdfifo_rstatus        (txdfifo_wstatus));
113
 
114
tx_control tx_ctrl(
115
                // Outputs
116
 
117
                .txdfifo_wdata          (txdfifo_wdata),
118
                .txdfifo_wstatus        (txdfifo_wstatus),
119
                .tx_ack                 (tx_ack),
120
 
121
                .clk                    (clk),
122
                .res_n                  (res_n),
123
                .tx_start               (tx_start),
124
                .tx_data                (tx_data),
125
                .tx_data_valid          (tx_data_valid));
126
 
127
 
128
 
129
endmodule
130
`default_nettype wire

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.