URL
https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk
bus2ip_clk
bus2ip_clk
bus2ip_resetn
bus2ip_resetn
bus2ip_mstrd_src_rdy_n
bus2ip_mstrd_src_rdy_n
bus2ip_mstrd_eof_n
bus2ip_mstrd_eof_n
bus2ip_data[31:0]
bus2ip_data[31:0]
ip2bus_mstrd_dst_dsc_n
ip2bus_mstrd_dst_dsc_n
u_dataout_std[31:0]
u_dataout_std[31:0]
HEXRADIX
c_dataout_std[31:0]
c_dataout_std[31:0]
u_data_valid_std_bit
u_data_valid_std_bit
c_data_valid_std_bit
c_data_valid_std_bit
rst_codmu
rst_codmu
clk_codmu
clk_codmu
rst_host
rst_host
clk_host
clk_host
din_host[31:0]
din_host[31:0]
wr_en_host
wr_en_host
rd_en_host
rd_en_host
dout_host[31:0]
dout_host[31:0]
full_host
full_host
overflow_host
overflow_host
empty_host
empty_host
underflow_host
underflow_host
addr[3:0]
addr[3:0]
ctrl[3:0]
ctrl[3:0]
trshold[7:0]
trshold[7:0]
bloksiz[15:0]
bloksiz[15:0]
filesiz[31:0]
filesiz[31:0]
statc[7:0]
statc[7:0]
statd[7:0]
statd[7:0]
statr[7:0]
statr[7:0]
statw[7:0]
statw[7:0]
cs
cs
rw
rw
address[3:0]
address[3:0]
control[31:0]
control[31:0]
clk
clk
clear
clear
bus_acknowledge_cc
bus_acknowledge_cc
bus_acknowledge_cu
bus_acknowledge_cu
bus_acknowledge_dc
bus_acknowledge_dc
bus_acknowledge_du
bus_acknowledge_du
wait_cu
wait_cu
wait_cc
wait_cc
wait_dc
wait_dc
wait_du
wait_du
u_datain[31:0]
u_datain[31:0]
c_datain[31:0]
c_datain[31:0]
u_dataout[31:0]
u_dataout[31:0]
c_dataout[31:0]
c_dataout[31:0]
finished_c
finished_c
finished_d
finished_d
compressing
compressing
flushing_c
flushing_c
flushing_d
flushing_d
decompressing
decompressing
u_data_valid
u_data_valid
c_data_valid
c_data_valid
decoding_overflow
decoding_overflow
coding_overflow
coding_overflow
crc_error
crc_error
interrupt_request
interrupt_request
interrupt_acknowledge
interrupt_acknowledge
bus_request_cc
bus_request_cc
bus_request_cu
bus_request_cu
bus_request_dc
bus_request_dc
bus_request_du
bus_request_du
cs_bit
cs_bit
rw_bit
rw_bit
address_bit[3:0]
address_bit[3:0]
control_std[31:0]
control_std[31:0]
clk_std
clk_std
clear_bit
clear_bit
resetn_std
resetn_std
bus_acknowledge_cc_bit
bus_acknowledge_cc_bit
bus_acknowledge_cu_bit
bus_acknowledge_cu_bit
bus_acknowledge_dc_bit
bus_acknowledge_dc_bit
bus_acknowledge_du_bit
bus_acknowledge_du_bit
wait_cu_bit
wait_cu_bit
wait_cc_bit
wait_cc_bit
wait_du_bit
wait_du_bit
c_datain_bit[31:0]
c_datain_bit[31:0]
finished_c_bit
finished_c_bit
finished_d_bit
finished_d_bit
u_data_valid_bit
u_data_valid_bit
c_data_valid_bit
c_data_valid_bit
interupt_acknwldge_bit
interupt_acknwldge_bit
bus_request_cc_bit
bus_request_cc_bit
bus_request_cu_bit
bus_request_cu_bit
bus_request_du_bit
bus_request_du_bit
reg_address[3:0]
reg_address[3:0]
reg_control[3:0]
reg_control[3:0]
reg_threshold[7:0]
reg_threshold[7:0]
reg_bytesize[15:0]
reg_bytesize[15:0]
cur_state1
cur_state1
next_state1
next_state1
slv_reg0[31:0]
slv_reg0[31:0]
reg_cr_test_bit
reg_cr_test_bit
reg_cr_31_to_28[3:0]
reg_cr_31_to_28[3:0]
reg_cr_18_to_12[6:0]
reg_cr_18_to_12[6:0]
reg_cr_11_to_0[11:0]
reg_cr_11_to_0[11:0]
u_datain_reg[31:0]
u_datain_reg[31:0]
c_datain_reg[31:0]
c_datain_reg[31:0]
int_ret_cu_size
int_ret_cu_size
int_ret_dc_size
int_ret_dc_size
clk_bit
clk_bit
wait_dc_bit
wait_dc_bit
bus_request_dc_bit
bus_request_dc_bit
fifo_read_signal
fifo_read_signal
fifo_data_out[31:0]
fifo_data_out[31:0]
HEXRADIX
c_datain_regx[31:0]
c_datain_regx[31:0]
HEXRADIX
bus2ip_mstrd_d[31:0]
bus2ip_mstrd_d[31:0]
HEXRADIX
u_datain_bit[31:0]
u_datain_bit[31:0]
HEXRADIX
fifo_data_in[31:0]
fifo_data_in[31:0]
HEXRADIX
cur_state
cur_state
next_state
next_state
cur_state_status
cur_state_status
next_state_status
next_state_status
din_codmu[31:0]
din_codmu[31:0]
wr_en_codmu
wr_en_codmu
rd_en_codmu
rd_en_codmu
dout_codmu[31:0]
dout_codmu[31:0]
full_codmu
full_codmu
overflow_codmu
overflow_codmu
empty_codmu
empty_codmu
rst_buffer
rst_buffer
underflow_codmu
underflow_codmu
wr_en_host_sm
wr_en_host_sm
wr_en_host_conc
wr_en_host_conc
u_datain_regx[31:0]
u_datain_regx[31:0]
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