Running: fuse.exe -relaunch -intstyle "ise" -incremental -lib "secureip" -o "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/testbench_isim_beh.exe" -prj "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/testbench_beh.prj" "work.testbench" ISim P.20131013 (signature 0x7708f090) Number of CPUs detected in this system: 4 Turning on mult-threading, number of parallel sub-compilation jobs: 8 Determining compilation order of HDL files Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/ipcore_dir/fifo_32x512.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/dzx/bit_arith_pkg.vhd" into library dzx Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/cam_bit.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/dzx/bit_utils_pkg.vhd" into library dzx Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/dzx/bit_arith_pkg_body.vhd" into library dzx Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/max_pbc_length_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mask_bit.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/length_selection_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/decode_mt_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/decode_miss_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/cam_byte.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/dzx/bit_utils_pkg_body.vhd" into library dzx Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/dzx/attributes_pkg.vhd" into library dzx Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/shift_literal.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/RLI_DR.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/RLI_DCU.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/RLI_CR.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/RLI_CCU.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_first.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_9.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_8.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_7.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_6.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_5.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_4.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_3.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_15.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_14.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_13.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_12.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_11.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_10.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_1.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/oda_cell_2_d_1.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/oda_cell_2_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/oda_cell_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/nfl_counters2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mld_dprop.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mld_decode.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/miss_type_coder.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mask_word.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/latch7.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/latch133.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/decomp_decode_4.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/decomp_assem_9.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/cam_word_zero.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/tech_package.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/sync_ram_register.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/sreg.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/rli_counter_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/rli_counter_c.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/RLI_coding_logic.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/reg_temp.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pointer_array.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/PIPELINE_R4.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/PIPELINE_R2_D.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/PIPELINE_R1_D.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/PIPELINE_R1.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/PIPELINE_R0.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/pc_generate.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/parser_register.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/parser_concatenator.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/parser.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/ov_latch.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/output_buffer_cu.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/oda_register_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/oda_register.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/ob_assembler.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/ob_assem.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mux_ram.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mt_coder.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mld_logic_3_2_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mld_logic_3_1_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mld_dprop_5.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mg_logic_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mc_mux_3d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/mc_mux_3c.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/location_equal.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/lc_assembler.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/latch98.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/latch6.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/input_counter_9bits.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/input_counter.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/input_buffer_cu.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/full_match_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/encode16_4.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/DECODING_BUFFER_CU_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/decode_logic_pbc.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/decode4_16_inv.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/count_delay.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/control_reg.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/CODING_BUFFER_CU.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/cm_assembler.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/cml_assembler.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/cam_array_zero.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/BUFFER_COUNTER_WRITE_9BITS.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/BUFFER_COUNTER_WRITE.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/BUFFER_COUNTER_READ_9BITS.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/BUFFER_COUNTER_READ.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/assembler_register.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/assembler.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/xil_lib/xil_comp.vhd" into library xil_lib Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/xil_lib/DP_RAM_XILINX_MASK.vhd" into library xil_lib Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/xil_lib/DP_RAM_XILINX_512.vhd" into library xil_lib Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/lib/xil_lib/DP_RAM_XILINX_256.vhd" into library xil_lib Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/reg_file_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/reg_file_c.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/parsing_unit.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/out_register.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/output_buffer_32_32.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4ca.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/input_buffer_32_32.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/DECODING_BUFFER_32_64_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/c_bs_counter_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/c_bs_counter_c.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/csm_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/csm_c_2.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/crc_unit_d_32.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/crc_unit_c_32.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/CODING_BUFFER_64_32.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/bsl_tc_2_d.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/bsl_tc_2_c.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/assembling_unit.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level1rd.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level1rc.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level1r.vhd" into library work Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd" into library work WARNING:HDLCompiler:946 - "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd" Line 284: Actual for formal port rst is neither a static name nor a globally static expression WARNING:HDLCompiler:946 - "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd" Line 302: Actual for formal port rst is neither a static name nor a globally static expression Parsing VHDL file "C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd" into library work Starting static elaboration Completed static elaboration Compiling package standard Compiling package std_logic_1164 Compiling package numeric_std Compiling package textio Compiling package std_logic_textio Compiling package std_logic_arith Compiling package std_logic_unsigned Compiling package bit_utils Compiling package bit_arith Compiling package xil_comp Compiling package tech_package Compiling architecture structural of entity PARSER_REGISTER [parser_register_default] Compiling architecture structural of entity PARSER [parser_default] Compiling architecture structural of entity PARSER_CONCATENATOR [parser_concatenator_default] Compiling architecture structural of entity PARSING_UNIT [parsing_unit_default] Compiling architecture structural of entity INPUT_BUFFER_CU [input_buffer_cu_default] Compiling architecture structural of entity INPUT_COUNTER [input_counter_default] Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V7_3_output_stage [\BLK_MEM_GEN_V7_3_output_stage("...] Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V7_3_output_stage [\BLK_MEM_GEN_V7_3_output_stage("...] Compiling architecture softecc_output_reg_stage_behavioral of entity BLK_MEM_GEN_V7_3_softecc_output_reg_stage [\BLK_MEM_GEN_V7_3_softecc_output...] Compiling architecture mem_module_behavioral of entity BLK_MEM_GEN_V7_3_mem_module [\BLK_MEM_GEN_V7_3_mem_module("bl...] Compiling architecture behavioral of entity BLK_MEM_GEN_V7_3 [\BLK_MEM_GEN_V7_3("blk_mem_gen_v...] Compiling architecture dp_ram_xilinx_256_a of entity DP_RAM_XILINX_256 [dp_ram_xilinx_256_default] Compiling architecture structural of entity INPUT_BUFFER_32_32 [input_buffer_32_32_default] Compiling architecture crc1 of entity CRC_UNIT_C_32 [crc_unit_c_32_default] Compiling package attributes Compiling architecture latch of entity SREG [sreg_default] Compiling architecture dec of entity MLD_DECODE [mld_decode_default] Compiling architecture decide_3 of entity MLD_LOGIC_3_1_2 [mld_logic_3_1_2_default] Compiling architecture structural of entity PIPELINE_R0 [pipeline_r0_default] Compiling architecture down of entity MLD_DPROP [mld_dprop_default] Compiling architecture decide_3 of entity MLD_LOGIC_3_2_2 [mld_logic_3_2_2_default] Compiling architecture multiplex_3 of entity MC_MUX_3C [mc_mux_3c_default] Compiling architecture structural of entity ODA_CELL_2 [oda_cell_2_default] Compiling architecture structural of entity ODA_REGISTER [oda_register_default] Compiling architecture count3 of entity NFL_COUNTERS2 [nfl_counters2_default] Compiling architecture down_2 of entity MLD_DPROP_5 [mld_dprop_5_default] Compiling architecture structural of entity FULL_MATCH_D [full_match_d_default] Compiling architecture bit1 of entity CAM_BIT [cam_bit_default] Compiling architecture byte1 of entity CAM_BYTE [cam_byte_default] Compiling architecture word1 of entity CAM_WORD_ZERO [cam_word_zero_default] Compiling architecture bit1 of entity MASK_BIT [mask_bit_default] Compiling architecture word1 of entity MASK_WORD [mask_word_default] Compiling architecture array1 of entity CAM_ARRAY_ZERO [cam_array_zero_default] Compiling architecture structural of entity PIPELINE_R1 [pipeline_r1_default] Compiling architecture enc2 of entity ENCODE16_4 [encode16_4_default] Compiling architecture structural of entity COUNT_DELAY [count_delay_default] Compiling architecture structural of entity RLI_COUNTER_C [rli_counter_c_default] Compiling architecture huffman of entity MT_CODER [mt_coder_default] Compiling architecture noshifter of entity CM_ASSEMBLER [cm_assembler_default] Compiling architecture huffman of entity MISS_TYPE_CODER [miss_type_coder_default] Compiling architecture first of entity LC_ASSEMBLER [lc_assembler_default] Compiling architecture shifter of entity CML_ASSEMBLER [cml_assembler_default] Compiling architecture flip_flop of entity LATCH98 [latch98_default] Compiling architecture flip_flop of entity LATCH6 [latch6_default] Compiling architecture structural of entity RLI_CR [rli_cr_default] Compiling architecture structural of entity RLI_CCU [rli_ccu_default] Compiling architecture structural of entity RLI_coding_logic [rli_coding_logic_default] Compiling architecture structural of entity PIPELINE_R4 [pipeline_r4_default] Compiling architecture assemble2 of entity OB_ASSEMBLER [ob_assembler_default] Compiling architecture flip_flop of entity OV_LATCH [ov_latch_default] Compiling architecture phased2 of entity PC_GENERATE [pc_generate_default] Compiling architecture cg_assembly of entity CG_ASSEMBLY [cg_assembly_default] Compiling architecture level2_4ca of entity level2_4ca [level2_4ca_default] Compiling architecture state of entity CSM_C_2 [csm_c_2_default] Compiling architecture counter of entity BSL_TC_2_C [bsl_tc_2_c_default] Compiling architecture latch of entity CONTROL_REG [control_reg_default] Compiling architecture latch of entity REG_FILE_C [reg_file_c_default] Compiling architecture structural of entity C_BS_COUNTER_C [c_bs_counter_c_default] Compiling architecture structural of entity CODING_BUFFER_CU [coding_buffer_cu_default] Compiling architecture structural of entity BUFFER_COUNTER_READ [buffer_counter_read_default] Compiling architecture structural of entity BUFFER_COUNTER_WRITE [buffer_counter_write_default] Compiling architecture structural of entity CODING_BUFFER_64_32 [coding_buffer_64_32_default] Compiling architecture level1_1 of entity level1rc [level1rc_default] Compiling architecture latch of entity OUT_REGISTER [out_register_default] Compiling architecture crc1 of entity CRC_UNIT_D_32 [crc_unit_d_32_default] Compiling architecture structural of entity OUTPUT_BUFFER_CU [output_buffer_cu_default] Compiling architecture structural of entity INPUT_COUNTER_9BITS [input_counter_9bits_default] Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V7_3_output_stage [\BLK_MEM_GEN_V7_3_output_stage("...] Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V7_3_output_stage [\BLK_MEM_GEN_V7_3_output_stage("...] Compiling architecture softecc_output_reg_stage_behavioral of entity BLK_MEM_GEN_V7_3_softecc_output_reg_stage [\BLK_MEM_GEN_V7_3_softecc_output...] Compiling architecture mem_module_behavioral of entity BLK_MEM_GEN_V7_3_mem_module [\BLK_MEM_GEN_V7_3_mem_module("bl...] Compiling architecture behavioral of entity BLK_MEM_GEN_V7_3 [\BLK_MEM_GEN_V7_3("blk_mem_gen_v...] Compiling architecture dp_ram_xilinx_512_a of entity DP_RAM_XILINX_512 [dp_ram_xilinx_512_default] Compiling architecture structural of entity OUTPUT_BUFFER_32_32 [output_buffer_32_32_default] Compiling architecture structural of entity ASSEMBLER_REGISTER [assembler_register_default] Compiling architecture assemble2 of entity ASSEMBLER [assembler_default] Compiling architecture structural of entity ASSEMBLING_UNIT [assembling_unit_default] Compiling architecture assemble of entity OB_ASSEM [ob_assem_default] Compiling architecture latch of entity REG_TEMP [reg_temp_default] Compiling architecture multiplex_3 of entity MUX_RAM [mux_ram_default] Compiling architecture structural of entity ODA_CELL_2_D [oda_cell_2_d_default] Compiling architecture structural of entity ODA_CELL_2_D_1 [oda_cell_2_d_1_default] Compiling architecture structural of entity ODA_REGISTER_D [oda_register_d_default] Compiling architecture multiplex_3 of entity MC_MUX_3D [mc_mux_3d_default] Compiling architecture move_2 of entity MG_LOGIC_2 [mg_logic_2_default] Compiling architecture dec1 of entity DECODE4_16_inv [decode4_16_inv_default] Compiling architecture structural of entity PIPELINE_R1_D [pipeline_r1_d_default] Compiling architecture structural of entity PIPELINE_R2_D [pipeline_r2_d_default] Compiling architecture latch of entity SYNC_RAM_REGISTER [sync_ram_register_default] Compiling architecture equality of entity LOCATION_EQUAL [location_equal_default] Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V7_3_output_stage [\BLK_MEM_GEN_V7_3_output_stage("...] Compiling architecture output_stage_behavioral of entity BLK_MEM_GEN_V7_3_output_stage [\BLK_MEM_GEN_V7_3_output_stage("...] Compiling architecture softecc_output_reg_stage_behavioral of entity BLK_MEM_GEN_V7_3_softecc_output_reg_stage [\BLK_MEM_GEN_V7_3_softecc_output...] Compiling architecture mem_module_behavioral of entity BLK_MEM_GEN_V7_3_mem_module [\BLK_MEM_GEN_V7_3_mem_module("bl...] Compiling architecture behavioral of entity BLK_MEM_GEN_V7_3 [\BLK_MEM_GEN_V7_3("blk_mem_gen_v...] Compiling architecture dp_ram_xilinx_mask_a of entity DP_RAM_XILINX_MASK [dp_ram_xilinx_mask_default] Compiling architecture pointer1 of entity POINTER_FIRST [pointer_first_default] Compiling architecture pointer1 of entity POINTER_1 [pointer_1_default] Compiling architecture pointer1 of entity POINTER_2 [pointer_2_default] Compiling architecture pointer1 of entity POINTER_3 [pointer_3_default] Compiling architecture pointer1 of entity POINTER_4 [pointer_4_default] Compiling architecture pointer1 of entity POINTER_5 [pointer_5_default] Compiling architecture pointer1 of entity POINTER_6 [pointer_6_default] Compiling architecture pointer1 of entity POINTER_7 [pointer_7_default] Compiling architecture pointer1 of entity POINTER_8 [pointer_8_default] Compiling architecture pointer1 of entity POINTER_9 [pointer_9_default] Compiling architecture pointer1 of entity POINTER_10 [pointer_10_default] Compiling architecture pointer1 of entity POINTER_11 [pointer_11_default] Compiling architecture pointer1 of entity POINTER_12 [pointer_12_default] Compiling architecture pointer1 of entity POINTER_13 [pointer_13_default] Compiling architecture pointer1 of entity POINTER_14 [pointer_14_default] Compiling architecture pointer1 of entity POINTER_15 [pointer_15_default] Compiling architecture array1 of entity POINTER_ARRAY [pointer_array_default] Compiling architecture structural of entity RLI_COUNTER_D [rli_counter_d_default] Compiling architecture flip_flop of entity LATCH7 [latch7_default] Compiling architecture flip_flop of entity LATCH133 [latch133_default] Compiling architecture dec_ass of entity DECOMP_ASSEM_9 [decomp_assem_9_default] Compiling architecture barrel of entity SHIFT_LITERAL [shift_literal_default] Compiling architecture structural of entity RLI_DR [rli_dr_default] Compiling architecture structural of entity RLI_DCU [rli_dcu_default] Compiling architecture structural of entity MAX_PBC_LENGTH_2 [max_pbc_length_2_default] Compiling architecture huffman of entity DECODE_MT_2 [decode_mt_2_default] Compiling architecture structural of entity LENGTH_SELECTION_2 [length_selection_2_default] Compiling architecture huffman of entity DECODE_MISS_2 [decode_miss_2_default] Compiling architecture nodecomp2 of entity DECOMP_DECODE_4 [decomp_decode_4_default] Compiling architecture decode_logic of entity DECODE_LOGIC_PBC [decode_logic_pbc_default] Compiling architecture level2_4d of entity level2_4d_pbc [level2_4d_pbc_default] Compiling architecture state of entity CSM_D [csm_d_default] Compiling architecture counter of entity BSL_TC_2_D [bsl_tc_2_d_default] Compiling architecture latch of entity REG_FILE_D [reg_file_d_default] Compiling architecture structural of entity C_BS_COUNTER_D [c_bs_counter_d_default] Compiling architecture structural of entity DECODING_BUFFER_CU_2 [decoding_buffer_cu_2_default] Compiling architecture structural of entity BUFFER_COUNTER_WRITE_9BITS [buffer_counter_write_9bits_defau...] Compiling architecture structural of entity BUFFER_COUNTER_READ_9BITS [buffer_counter_read_9bits_defaul...] Compiling architecture structural of entity DECODING_BUFFER_32_64_2 [decoding_buffer_32_64_2_default] Compiling architecture level1_1 of entity level1rd [level1rd_default] Compiling architecture level1_1 of entity level1r [level1r_default] Compiling architecture behavioral of entity fifo_generator_v9_3_bhv_as [\fifo_generator_v9_3_bhv_as(32,"...] Compiling architecture behavioral of entity fifo_generator_v9_3_conv [\fifo_generator_v9_3_conv(0,0,20...] Compiling architecture behavioral of entity fifo_generator_v9_3 [\fifo_generator_v9_3(0,0,20,"Bla...] Compiling architecture fifo_32x512_a of entity fifo_32x512 [fifo_32x512_default] Compiling architecture behavioral of entity xmatch_controller [xmatch_controller_default] Compiling architecture behavior of entity testbench Time Resolution for simulation is 1ps. Waiting for 112 sub-compilation(s) to finish... Compiled 295 VHDL Units Built simulation executable C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/testbench_isim_beh.exe Fuse Memory Usage: 57432 KB Fuse CPU Usage: 3306 ms