############################################################## # # Xilinx Core Generator version 14.7 # Date: Fri Jul 17 05:54:55 2015 # ############################################################## # # This file contains the customisation parameters for a # Xilinx CORE Generator IP GUI. It is strongly recommended # that you do not manually alter this file as it may cause # unexpected and unsupported behavior. # ############################################################## # # Generated from component: xilinx.com:ip:fifo_generator:9.3 # ############################################################## # # BEGIN Project Options SET addpads = false SET asysymbol = true SET busformat = BusFormatAngleBracketNotRipped SET createndf = false SET designentry = VHDL SET device = xc7vx485t SET devicefamily = virtex7 SET flowvendor = Other SET formalverification = false SET foundationsym = false SET implementationfiletype = Ngc SET package = ffg1761 SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -2 SET verilogsim = false SET vhdlsim = true # END Project Options # BEGIN Select SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 # END Select # BEGIN Parameters CSET add_ngc_constraint_axi=false CSET almost_empty_flag=false CSET almost_full_flag=true CSET aruser_width=1 CSET awuser_width=1 CSET axi_address_width=32 CSET axi_data_width=64 CSET axi_type=AXI4_Stream CSET axis_type=FIFO CSET buser_width=1 CSET clock_enable_type=Slave_Interface_Clock_Enable CSET clock_type_axi=Common_Clock CSET component_name=fifo_32x512 CSET data_count=false CSET data_count_width=20 CSET disable_timing_violations=false CSET disable_timing_violations_axi=false CSET dout_reset_value=0 CSET empty_threshold_assert_value=2 CSET empty_threshold_assert_value_axis=1022 CSET empty_threshold_assert_value_rach=1022 CSET empty_threshold_assert_value_rdch=1022 CSET empty_threshold_assert_value_wach=1022 CSET empty_threshold_assert_value_wdch=1022 CSET empty_threshold_assert_value_wrch=1022 CSET empty_threshold_negate_value=3 CSET enable_aruser=false CSET enable_awuser=false CSET enable_buser=false CSET enable_common_overflow=false CSET enable_common_underflow=false CSET enable_data_counts_axis=false CSET enable_data_counts_rach=false CSET enable_data_counts_rdch=false CSET enable_data_counts_wach=false CSET enable_data_counts_wdch=false CSET enable_data_counts_wrch=false CSET enable_ecc=false CSET enable_ecc_axis=false CSET enable_ecc_rach=false CSET enable_ecc_rdch=false CSET enable_ecc_wach=false CSET enable_ecc_wdch=false CSET enable_ecc_wrch=false CSET enable_read_channel=false CSET enable_read_pointer_increment_by2=false CSET enable_reset_synchronization=true CSET enable_ruser=false CSET enable_tdata=false CSET enable_tdest=false CSET enable_tid=false CSET enable_tkeep=false CSET enable_tlast=false CSET enable_tready=true CSET enable_tstrobe=false CSET enable_tuser=false CSET enable_write_channel=false CSET enable_wuser=false CSET fifo_application_type_axis=Data_FIFO CSET fifo_application_type_rach=Data_FIFO CSET fifo_application_type_rdch=Data_FIFO CSET fifo_application_type_wach=Data_FIFO CSET fifo_application_type_wdch=Data_FIFO CSET fifo_application_type_wrch=Data_FIFO CSET fifo_implementation=Independent_Clocks_Block_RAM CSET fifo_implementation_axis=Common_Clock_Block_RAM CSET fifo_implementation_rach=Common_Clock_Block_RAM CSET fifo_implementation_rdch=Common_Clock_Block_RAM CSET fifo_implementation_wach=Common_Clock_Block_RAM CSET fifo_implementation_wdch=Common_Clock_Block_RAM CSET fifo_implementation_wrch=Common_Clock_Block_RAM CSET full_flags_reset_value=1 CSET full_threshold_assert_value=1048573 CSET full_threshold_assert_value_axis=1023 CSET full_threshold_assert_value_rach=1023 CSET full_threshold_assert_value_rdch=1023 CSET full_threshold_assert_value_wach=1023 CSET full_threshold_assert_value_wdch=1023 CSET full_threshold_assert_value_wrch=1023 CSET full_threshold_negate_value=1048572 CSET id_width=4 CSET inject_dbit_error=false CSET inject_dbit_error_axis=false CSET inject_dbit_error_rach=false CSET inject_dbit_error_rdch=false CSET inject_dbit_error_wach=false CSET inject_dbit_error_wdch=false CSET inject_dbit_error_wrch=false CSET inject_sbit_error=false CSET inject_sbit_error_axis=false CSET inject_sbit_error_rach=false CSET inject_sbit_error_rdch=false CSET inject_sbit_error_wach=false CSET inject_sbit_error_wdch=false CSET inject_sbit_error_wrch=false CSET input_data_width=32 CSET input_depth=1048576 CSET input_depth_axis=1024 CSET input_depth_rach=16 CSET input_depth_rdch=1024 CSET input_depth_wach=16 CSET input_depth_wdch=1024 CSET input_depth_wrch=16 CSET interface_type=Native CSET output_data_width=32 CSET output_depth=1048576 CSET overflow_flag=false CSET overflow_flag_axi=false CSET overflow_sense=Active_High CSET overflow_sense_axi=Active_High CSET performance_options=Standard_FIFO CSET programmable_empty_type=No_Programmable_Empty_Threshold CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold CSET programmable_full_type=No_Programmable_Full_Threshold CSET programmable_full_type_axis=No_Programmable_Full_Threshold CSET programmable_full_type_rach=No_Programmable_Full_Threshold CSET programmable_full_type_rdch=No_Programmable_Full_Threshold CSET programmable_full_type_wach=No_Programmable_Full_Threshold CSET programmable_full_type_wdch=No_Programmable_Full_Threshold CSET programmable_full_type_wrch=No_Programmable_Full_Threshold CSET rach_type=FIFO CSET rdch_type=FIFO CSET read_clock_frequency=1 CSET read_data_count=false CSET read_data_count_width=20 CSET register_slice_mode_axis=Fully_Registered CSET register_slice_mode_rach=Fully_Registered CSET register_slice_mode_rdch=Fully_Registered CSET register_slice_mode_wach=Fully_Registered CSET register_slice_mode_wdch=Fully_Registered CSET register_slice_mode_wrch=Fully_Registered CSET reset_pin=true CSET reset_type=Asynchronous_Reset CSET ruser_width=1 CSET synchronization_stages=2 CSET synchronization_stages_axi=2 CSET tdata_width=64 CSET tdest_width=4 CSET tid_width=8 CSET tkeep_width=4 CSET tstrb_width=4 CSET tuser_width=4 CSET underflow_flag=false CSET underflow_flag_axi=false CSET underflow_sense=Active_High CSET underflow_sense_axi=Active_High CSET use_clock_enable=false CSET use_dout_reset=true CSET use_embedded_registers=false CSET use_extra_logic=false CSET valid_flag=false CSET valid_sense=Active_High CSET wach_type=FIFO CSET wdch_type=FIFO CSET wrch_type=FIFO CSET write_acknowledge_flag=false CSET write_acknowledge_sense=Active_High CSET write_clock_frequency=1 CSET write_data_count=false CSET write_data_count_width=20 CSET wuser_width=1 # END Parameters # BEGIN Extra information MISC pkg_timestamp=2012-11-19T12:39:56Z # END Extra information GENERATE # CRC: 6ded5e94