URL
https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk
2
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/CODING_BUFFER - CODING_BUFFER_64_32 - STRUCTURAL
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/I_B - INPUT_BUFFER_32_32 - STRUCTURAL
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/P_U - PARSING_UNIT - STRUCTURAL
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/REG_FILE_1 - REG_FILE_C - LATCH
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/level2_4_1 - level2_4ca - level2_4ca
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/ASSEMBLING_UNIT_1 - ASSEMBLING_UNIT - STRUCTURAL
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/DECODING_BUFFER - DECODING_BUFFER_32_64_2 - STRUCTURAL
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/OUTPUT_BUFFER_32_32_1 - OUTPUT_BUFFER_32_32 - STRUCTURAL
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/REG_FILE_1 - REG_FILE_D - LATCH
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1/level2_4_1 - level2_4d_pbc - level2_4d
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd/xmatchpro - level1r - level1_1
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/CODING_BUFFER - CODING_BUFFER_64_32 - STRUCTURAL
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/I_B - INPUT_BUFFER_32_32 - STRUCTURAL
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/P_U - PARSING_UNIT - STRUCTURAL
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/REG_FILE_1 - REG_FILE_C - LATCH
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_c - level1rc - level1_1/level2_4_1 - level2_4ca - level2_4ca
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1/level1_d - level1rd - level1_1
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/inst_xmatch - level1r - level1_1
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd/xmatchpro - level1r - level1_1
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd/inst_xmatch - level1r - level1_1
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd/xmatchpro - level1r - level1_1
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd/xmatchpro - level1r - level1_1
xmatch_controller - Behavioral (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd)
0
0
000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000002c4000000020000000000000000000000000200000064ffffffff000000810000000300000002000002c40000000100000003000000000000000100000003
true
xmatch_controller - Behavioral (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/fifo_test.vhd)
1
Configure Target Device
Design Utilities
Design Utilities/Compile HDL Simulation Libraries
Implement Design/Map
Implement Design/Place & Route
Implement Design/Translate
Synthesize - XST
User Constraints
0
0
000000ff0000000000000001000000010000000000000000000000000000000000000000000000017f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000017f0000000100000000
false
1
0
0
000000ff0000000000000001000000000000000001000000000000000000000000000000000000040a000000040101000100000000000000000000000064ffffffff000000810000000000000004000002690000000100000000000000d70000000100000000000000660000000100000000000000640000000100000000
false
assembler.vhd
1
dzx
0
0
000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
false
dzx
1
User Constraints
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000263000000010000000100000000000000000000000064ffffffff000000810000000000000001000002630000000100000000
false
2
/TB_LEVEL1cr - TB1cr C:|mohd|codmu_project|devl|xmatch_sim3|tb_level1cr.vhd
/TB_LEVEL1cr - TB1cr C:|mohd|codmu_project|devl|xmatch_sim5|tb_level1cr.vhd
/TB_LEVEL1cr - TB1cr C:|mohd|codmu_project|devl|xmatch_sim7|tb_level1cr.vhd
/fifo_test_tb - behavior C:|mohd|Fifo_test|fifo_test_tb.vhd/uut - fifo_test - Behavioral
/fifo_test_tb - behavior C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test_tb.vhd
/fifo_test_tb - behavior C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test_tb.vhd
/fifo_test_tb - behavior C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test_tb.vhd
/testbench - behavior C:|Users|eejlny|projects|xmatch_sim7|xmatch_sim7|tb.vhd
/testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim3|tb.vhd
/testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim3|tb.vhd/uut - top - Behavioral
/testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim5|tb.vhd
/testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim5|tb.vhd/uut - xmatchpro - Behavioral/xmatchpro - level1r - level1_1
/testbench - behavior C:|mohd|codmu_project|devl|xmatch_sim7|tb.vhd/uut - xmatch_controller - Behavioral/xmatchpro - level1r - level1_1
/top - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd
/xmatch_controller - Behavioral C:|mohd|codmu_project|devl|xmatch_sim5|fifo_test.vhd
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim3|fifo_test.vhd
/xmatchpro - Behavioral C:|mohd|codmu_project|devl|xmatch_sim7|fifo_test.vhd
testbench - behavior (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd)
0
0
000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000de000000020000000000000000000000000200000064ffffffff000000810000000300000002000000de0000000100000003000000000000000100000003
true
testbench - behavior (C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/tb.vhd)
1
Design Utilities/Compile HDL Simulation Libraries
0
0
000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
false
1
ISim Simulator
0
0
000000ff0000000000000001000000010000000000000000000000000000000000000000000000017f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000017f0000000100000000
false
ISim Simulator
1
Configure Target Device
Design Utilities/Compile HDL Simulation Libraries
Implement Design
Synthesize - XST
User Constraints
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000219000000010000000100000000000000000000000064ffffffff000000810000000000000001000002190000000100000000
false
000000ff00000000000000020000011b0000011b01000000050100000002
Behavioral Simulation
1
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000196000000010000000100000000000000000000000064ffffffff000000810000000000000001000001960000000100000000
false
1
0
0
000000ff00000000000000010000000100000000000000000000000000000000000000000000000122000000010000000100000000000000000000000064ffffffff000000810000000000000001000001220000000100000000
false
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