URL
https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk
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( ) * + , - . 2 3 r s t std_standard C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd level2_4d_pbc level2_4d ieee_p_2592010699 xil_lib_p_2638593979 work_p_0296486974 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd clk C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd clear C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd reset C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd decomp C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_enable C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd decoding_underflow C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd finish C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd c_datain C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_dataout C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd mask C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_data_valid C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd overflow_control C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd underflow dzx_p_3308480207 dzx_p_1715488261 dzx_p_3728046382 ieee_p_3499444699 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd c_din C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd ram_data C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd ram_mask C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd ram_data_aux C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd ram_mask_aux C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_full_hit C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_data C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_mask C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mloc C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mtype C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_move C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_dout C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd enabled C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_data_p1 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_mask_p1 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mtype_p1 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_data_p2 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_mask_p2 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mtype_p2 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd mloc_p1 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mloc_p2 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd mloc C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_full_hit_p1 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_full_hit_p2 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_enable_p2 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_int C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_int_aux C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_drop C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd rl_detected_d C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd rl_count_d C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd end_count_d C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd count_enable_d C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_dout_r C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_mask_r C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd wait_data C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd write_address C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd read_address C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd write_address_memory C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd read_address_memory C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd clk_memory C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_dout_r_memory C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd enabled_memory_rd C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd enabled_memory_wr C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_pointer C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mtype_mem C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_mask_r_memory C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd assem_data C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd assem_mask C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_mtype_out C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_data_out C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd d_lit_mask_out C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_dout_r_int C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_mask_r_int C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd equal C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd u_data_valid_int C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd read_address_out C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd write_address_out C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd write_address_int C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd tsmc_cena_n C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd tsmc_cenb_n C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd tsmc_wena_n C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd tsmc_wenb_n C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :523 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :525 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd ram_data ram_mask match_type literal_data literal_mask dout mout a_1158458395 OB_ASSEM_1 work_a_1158458395_3100604312 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd data_in mask_in clk clear reset enable mask_out data_out a_0687040014 REG_TEMP1 work_a_0687040014_1241093336 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd ram_mask ram_data reg_data reg_mask equal assem_data assem_mask a_3978272650 MUX_RAM1 work_a_3978272650_2808840082 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move_in move_enable control clk clear reset move_out a_2574286743 ODA_REGISTER_1 work_a_2574286743_1181938964 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd b enabled y a_0515342765 MC_MUX_1 work_a_0515342765_2808840082 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd din dout a_3543352438 MOVE_GENERATION work_a_3543352438_0520823001 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd move match_loc full_hit a_1123029535 MG_LOGIC_1 work_a_1123029535_2364406165 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd match_loc_in match_loc_out a_1564650580 DECODE4_17 work_a_1564650580_1781843606 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd full_hit_in match_type_in match_loc_in lit_data_in lit_mask_in move_enable_d_in clear reset clk full_hit_out match_type_out match_loc_out lit_data_out lit_mask_out move_enable_d_out a_1400021221 PIPELINE_R1_D_1 work_a_1400021221_1181938964 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd match_loc_in_d match_type_in lit_data_in lit_mask_in move_enable_d_in full_hit_in clear reset clk match_loc_out_d match_type_out lit_data_out lit_mask_out full_hit_out move_enable_d_out a_3398485732 PIPELINE_R2_D_1 work_a_3398485732_1181938964 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd write_address_in match_type_in literal_data_in literal_mask_in u_data_valid_in enable clear reset clk write_address_out match_type_out literal_data_out literal_mask_out u_data_valid_out a_1339860356 SYNC_RAM_REGISTER1 work_a_1339860356_1241093336 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd write_address_in read_address_in clk clear reset enable write_address_out read_address_out equal a_2199942654 LOCATION_EQUAL1 work_a_2199942654_2855297284 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd addra clka addrb clkb dina wea enb doutb a_2536342394 RAM_DIC xil_lib_a_2536342394_0793580669 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :760 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :761 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :762 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :768 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd addra clka addrb clkb dina wea enb doutb a_2622353874 MASK_ARRAY xil_lib_a_2622353874_0189569759 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :808 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :809 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :810 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :811 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :812 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :813 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :814 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :818 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :819 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd previous move move_enable sel_write sel_read clear reset clk write_address read_address a_1343409402 POINTER_ARRAY_1 work_a_1343409402_2984478664 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd load data enable_d clear reset clk end_count a_0326967633 RLI_D work_a_0326967633_1181938964 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd literal_data match_type match_loc mask wait_data d_full_hit rl_detected rl_count underflow count_enable end_count din decomp clear reset enable decoding_underflow overflow_control clk a_1772052966 DECODE_LOGIC_1 work_a_1772052966_3569083931 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :882 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :883 C:/Users/eejlny/projects/xmatch_sim7/xmatch_sim7/src/level2_4d_pbc.vhd :884 ? @ ? @ isim/testbench_isim_beh.exe.sim/work/a_3022590147_3381363857.didat
