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[/] [xulalx25soc/] [trunk/] [rtl/] [memdev.v] - Blame information for rev 2

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    memdev.v
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//
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// Project:     XuLA2 board
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//
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// Purpose:     This file is really simple: it creates an on-chip memory,
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//              accessible via the wishbone bus, that can be used in this
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//      project.  The memory has single cycle access--although getting to the
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//      memory from the ZipCPU may cost another cycle or two in access.  Either
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//      way, operations can be pipelined for greater speed.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module  memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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                o_wb_ack, o_wb_stall, o_wb_data);
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        parameter       AW=15, DW=32;
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        input                           i_clk, i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [(AW-1):0]       i_wb_addr;
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        input           [(DW-1):0]       i_wb_data;
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(DW-1):0]       o_wb_data;
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        reg     [(DW-1):0]       mem     [0:((1<<AW)-1)];
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        always @(posedge i_clk)
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                o_wb_data <= mem[i_wb_addr];
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        always @(posedge i_clk)
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                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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                        mem[i_wb_addr] <= i_wb_data;
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        always @(posedge i_clk)
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                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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        assign  o_wb_stall = 1'b0;
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endmodule

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