OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [wbuidleint.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbuidleint.v
4
//
5
// Project:     XuLA2 board
6
//
7
// Purpose:     Creates an output for the interface, inserting idle words and
8
//              words indicating an interrupt has taken place into the output
9
//      stream.  Henceforth, the output means more than just bus transaction
10
//      results.  It may mean there is no bus transaction result to report,
11
//      or that an interrupt has taken place.
12
//
13
//
14
// Creator:     Dan Gisselquist, Ph.D.
15
//              Gisselquist Technology, LLC
16
//
17
////////////////////////////////////////////////////////////////////////////////
18
//
19
// Copyright (C) 2015, Gisselquist Technology, LLC
20
//
21
// This program is free software (firmware): you can redistribute it and/or
22
// modify it under the terms of  the GNU General Public License as published
23
// by the Free Software Foundation, either version 3 of the License, or (at
24
// your option) any later version.
25
//
26
// This program is distributed in the hope that it will be useful, but WITHOUT
27
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
28
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
29
// for more details.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
////////////////////////////////////////////////////////////////////////////////
36
//
37
//
38
module  wbuidleint(i_clk, i_stb, i_codword, i_cyc, i_busy, i_int,
39
                o_stb, o_codword, o_busy,
40
                i_tx_busy);
41
        input                   i_clk;
42
        // From the FIFO following the bus executor
43
        input                   i_stb;
44
        input           [35:0]   i_codword;
45
        // From the rest of the board
46
        input                   i_cyc, i_busy, i_int;
47
        // To the next stage
48
        output  reg             o_stb;
49
        output  reg     [35:0]   o_codword;
50
        output  reg             o_busy;
51
        // Is the next stage busy?
52
        input                   i_tx_busy;
53
 
54
        reg     int_request, int_sent;
55
        initial int_request = 1'b0;
56
        always @(posedge i_clk)
57
                if((o_stb)&&(~i_tx_busy)&&(o_codword[35:30]==6'h4))
58
                        int_request <= i_int;
59
                else
60
                        int_request <= (int_request)||(i_int);
61
 
62
 
63
        // Now, for the idle counter
64
        wire            idle_expired;
65
        reg             idle_state;
66
        reg     [35:0]   idle_counter;
67
        initial idle_counter = 36'h0000;
68
        always @(posedge i_clk)
69
                if ((i_stb)||(o_stb))
70
                        idle_counter <= 36'h000;
71
                else if (~idle_counter[35])
72
                        idle_counter <= idle_counter + 36'd43;
73
 
74
        initial idle_state = 1'b0;
75
        always @(posedge i_clk)
76
                if ((o_stb)&&(~i_tx_busy)&&(o_codword[35:31]==5'h0))
77
                        idle_state <= 1'b1;
78
                else if (~idle_counter[35])
79
                        idle_state <= 1'b0;
80
 
81
        assign  idle_expired = (~idle_state)&&(idle_counter[35]);
82
 
83
        initial o_stb  = 1'b0;
84
        initial o_busy = 1'b0;
85
        always @(posedge i_clk)
86
                if ((o_stb)&&(i_tx_busy))
87
                begin
88
                        o_busy <= 1'b1;
89
                end else if (o_stb) // and not i_tx_busy
90
                begin
91
                        // Idle one clock before becoming not busy
92
                        o_stb <= 1'b0;
93
                        o_busy <= 1'b1;
94
                end else if (o_busy)
95
                        o_busy <= 1'b0;
96
                else if (i_stb) // and (~o_busy)&&(~o_stb)
97
                begin // On a valid output, just send it out
98
                        // We'll open this strobe, even if the transmitter
99
                        // is busy, just 'cause we might otherwise lose it
100
                        o_codword <= i_codword;
101
                        o_stb <= 1'b1;
102
                        o_busy <= 1'b1;
103
                end else if ((int_request)&&(~int_sent))
104
                begin
105
                        o_stb <= 1'b1;
106
                        o_codword <= { 6'h4, 30'h0000 }; // interrupt codeword
107
                        o_busy <= 1'b1;
108
                end else if (idle_expired)
109
                begin // Strobe, if we're not writing or our
110
                        // last command wasn't an idle
111
                        o_stb  <= 1'b1;
112
                        o_busy <= 1'b1;
113
                        if (i_cyc)
114
                                o_codword <= { 6'h1, 30'h0000 }; // idle codeword, bus busy
115
                        else
116
                                o_codword <= { 6'h0, 30'h0000 };
117
                end
118
 
119
        initial int_sent = 1'b0;
120
        always @(posedge i_clk)
121
                if ((int_request)&&((~o_stb)&&(~o_busy)&&(~i_stb)))
122
                        int_sent <= 1'b1;
123
                else if (~i_int)
124
                        int_sent <= 1'b0;
125
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.