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dgisselq |
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename: zipdbg.cpp
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdlib.h>
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#include <signal.h>
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#include <time.h>
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#include <unistd.h>
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#include <ctype.h>
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#include <ncurses.h>
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#include "zopcodes.h"
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#include "zparser.h"
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#include "devbus.h"
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#include "regdefs.h"
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#include "usbi.h"
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#include "port.h"
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#define CMD_REG 0
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#define CMD_DATA 1
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#define CMD_HALT (1<<10)
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#define CMD_STALL (1<<9)
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#define CMD_STEP (1<<8)
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#define CMD_INT (1<<7)
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#define CMD_RESET (1<<6)
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#define KEY_ESCAPE 27
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#define KEY_RETURN 10
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#define CTRL(X) ((X)&0x01f)
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#define MAXERR 1000 // 1k cycles
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bool gbl_err = false;
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// No particular "parameters" need definition or redefinition here.
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class ZIPPY : public DEVBUS {
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typedef DEVBUS::BUSW BUSW;
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DEVBUS *m_fpga;
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int m_cursor;
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public:
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ZIPPY(DEVBUS *fpga) : m_fpga(fpga), m_cursor(0) {}
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void kill(void) { m_fpga->kill(); }
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void close(void) { m_fpga->close(); }
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void writeio(const BUSW a, const BUSW v) { m_fpga->writeio(a, v); }
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BUSW readio(const BUSW a) { return m_fpga->readio(a); }
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void readi(const BUSW a, const int len, BUSW *buf) {
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return m_fpga->readi(a, len, buf); }
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void readz(const BUSW a, const int len, BUSW *buf) {
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return m_fpga->readz(a, len, buf); }
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void writei(const BUSW a, const int len, const BUSW *buf) {
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return m_fpga->writei(a, len, buf); }
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void writez(const BUSW a, const int len, const BUSW *buf) {
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return m_fpga->writez(a, len, buf); }
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bool poll(void) { return m_fpga->poll(); }
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void usleep(unsigned ms) { m_fpga->usleep(ms); }
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void wait(void) { m_fpga->wait(); }
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bool bus_err(void) const { return m_fpga->bus_err(); }
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void reset_err(void) { m_fpga->reset_err(); }
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void clear(void) { m_fpga->clear(); }
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void reset(void) { writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT); }
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void step(void) { writeio(R_ZIPCTRL, CPU_STEP); }
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void go(void) { writeio(R_ZIPCTRL, CPU_GO); }
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void halt(void) { writeio(R_ZIPCTRL, CPU_HALT); }
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bool stalled(void) { return ((readio(R_ZIPCTRL)&CPU_STALL)==0); }
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void showval(int y, int x, const char *lbl, unsigned int v, bool c) {
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if (c)
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mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
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else
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mvprintw(y,x, " %s: 0x%08x ", lbl, v);
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}
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void dispreg(int y, int x, const char *n, unsigned int v, bool c) {
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// 4,4,8,1 = 17 of 20, +2 = 18
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if (c)
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mvprintw(y, x, ">%s> 0x%08x<", n, v);
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else
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mvprintw(y, x, " %s: 0x%08x ", n, v);
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}
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void showins(int y, const char *lbl,
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const int gie, const unsigned int pc) {
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char line[80];
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unsigned int v;
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mvprintw(y, 0, "%s: 0x%08x", lbl, pc);
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if (gie) attroff(A_BOLD);
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else attron(A_BOLD);
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line[0] = '\0';
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try {
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v= readio(pc);
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zipi_to_string(v, line);
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printw(" 0x%08x", v);
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printw(" %-24s", &line[1]);
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} catch(BUSERR b) {
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printw(" 0x%08x %-24s", b.addr, "(Bus Error)");
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}
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attroff(A_BOLD);
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}
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unsigned int cmd_read(unsigned int a) {
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int errcount = 0;
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if (gbl_err)
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return 0;
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writeio(R_ZIPCTRL, CMD_HALT|(a&0x3f));
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while(((readio(R_ZIPCTRL) & CPU_STALL) == 0)&&(errcount < MAXERR))
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errcount++;
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if (errcount < MAXERR)
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return readio(R_ZIPDATA);
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else {
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gbl_err = true;
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return 0;
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}
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}
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void cmd_write(unsigned int a, int v) {
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if (gbl_err)
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return;
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int errcount = 0;
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writeio(R_ZIPCTRL, CMD_HALT|(a&0x3f));
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while(((readio(R_ZIPCTRL) & CPU_STALL) == 0)&&(errcount < MAXERR))
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errcount++;
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if (errcount < MAXERR)
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writeio(R_ZIPDATA, (unsigned int)v);
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else
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gbl_err = true;
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}
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void read_state(void) {
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int ln= 0;
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bool gie;
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if (m_cursor < 0)
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m_cursor = 0;
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else if (m_cursor >= 44)
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m_cursor = 43;
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mvprintw(ln,0, "Peripherals");
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mvprintw(ln,40,"%-40s", "CPU State: ");
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{
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unsigned int v = readio(R_ZIPCTRL);
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mvprintw(ln,51, "");
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if (v & 0x010000)
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printw("EXT-INT ");
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if ((v & 0x003000) == 0x03000)
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printw("Halted ");
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else if (v & 0x001000)
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printw("Sleeping ");
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else if (v & 0x002000)
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printw("Supervisor Mod ");
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if (v & 0x008000)
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printw("Break-Enabled ");
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if (v & 0x000080)
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printw("PIC Enabled ");
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} ln++;
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showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
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showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
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showval(ln,40, "WBUS", cmd_read(32+ 2), (m_cursor==2));
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showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
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ln++;
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showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
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showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
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showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
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showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
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ln++;
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showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
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showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
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showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
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showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
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ln++;
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ln++;
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unsigned int cc = cmd_read(14);
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gie = (cc & 0x020);
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if (gie)
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attroff(A_BOLD);
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else
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attron(A_BOLD);
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mvprintw(ln, 0, "Supervisor Registers");
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ln++;
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dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
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dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
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dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
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dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
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dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
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dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
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| 228 |
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dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
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dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
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| 231 |
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dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
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dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
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dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
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dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
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| 236 |
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dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
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dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
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| 238 |
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| 239 |
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mvprintw(ln,40, "%csCC :%s%s%s%s%s%s%s%s",
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| 240 |
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(m_cursor==26)?'>':' ',
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| 241 |
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(cc & 0x100)?"TP":" ",
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| 242 |
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(cc & 0x040)?"ST":" ",
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| 243 |
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(cc & 0x020)?"IE":" ",
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| 244 |
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(cc & 0x010)?"SL":" ",
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| 245 |
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(cc&8)?"V":" ",
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| 246 |
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(cc&4)?"N":" ",
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| 247 |
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(cc&2)?"C":" ",
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| 248 |
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(cc&1)?"Z":" ");
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| 249 |
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dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
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| 250 |
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ln++;
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| 251 |
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| 252 |
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if (gie)
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| 253 |
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attron(A_BOLD);
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| 254 |
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else
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| 255 |
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attroff(A_BOLD);
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| 256 |
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mvprintw(ln, 0, "User Registers"); ln++;
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| 257 |
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dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
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| 258 |
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dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
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| 259 |
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dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
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| 260 |
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dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
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| 261 |
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| 262 |
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dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
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| 263 |
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dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
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| 264 |
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dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
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| 265 |
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dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
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| 266 |
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| 267 |
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dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
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| 268 |
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dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
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| 269 |
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dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
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| 270 |
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dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
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| 271 |
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| 272 |
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dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
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| 273 |
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dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
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| 274 |
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cc = cmd_read(30);
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| 275 |
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mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
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| 276 |
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(m_cursor == 42)?'>':' ',
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| 277 |
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(cc&0x100)?"TP":" ",
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| 278 |
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(cc&0x040)?"ST":" ",
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| 279 |
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(cc&0x020)?"IE":" ",
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| 280 |
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(cc&0x010)?"SL":" ",
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| 281 |
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(cc&8)?"V":" ",
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| 282 |
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(cc&4)?"N":" ",
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| 283 |
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(cc&2)?"C":" ",
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| 284 |
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(cc&1)?"Z":" ");
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| 285 |
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dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
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| 286 |
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| 287 |
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attroff(A_BOLD);
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| 288 |
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ln+=2;
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| 289 |
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| 290 |
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ln+=3;
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| 291 |
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BUSW pc = cmd_read((gie)?31:15);
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| 292 |
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showins(ln, "I ", gie, pc+2); ln++;
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| 293 |
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showins(ln, "Dc", gie, pc+1); ln++;
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| 294 |
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showins(ln, "Op", gie, pc ); ln++;
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| 295 |
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showins(ln, "Al", gie, pc-1); ln++;
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| 296 |
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}
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| 297 |
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| 298 |
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void cursor_up(void) {
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| 299 |
|
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if (m_cursor > 3)
|
| 300 |
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m_cursor -= 4;
|
| 301 |
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} void cursor_down(void) {
|
| 302 |
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if (m_cursor < 40)
|
| 303 |
|
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m_cursor += 4;
|
| 304 |
|
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} void cursor_left(void) {
|
| 305 |
|
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if (m_cursor > 0)
|
| 306 |
|
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m_cursor--;
|
| 307 |
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else m_cursor = 43;
|
| 308 |
|
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} void cursor_right(void) {
|
| 309 |
|
|
if (m_cursor < 43)
|
| 310 |
|
|
m_cursor++;
|
| 311 |
|
|
else m_cursor = 0;
|
| 312 |
|
|
}
|
| 313 |
|
|
|
| 314 |
|
|
int cursor(void) { return m_cursor; }
|
| 315 |
|
|
};
|
| 316 |
|
|
|
| 317 |
|
|
FPGA *m_fpga;
|
| 318 |
|
|
|
| 319 |
|
|
void get_value(ZIPPY *zip) {
|
| 320 |
|
|
int wy, wx, ra;
|
| 321 |
|
|
int c = zip->cursor();
|
| 322 |
|
|
|
| 323 |
|
|
wx = (c & 0x03) * 20 + 9 + 1;
|
| 324 |
|
|
wy = (c >> 2);
|
| 325 |
|
|
if (wy >= 3+4)
|
| 326 |
|
|
wy++;
|
| 327 |
|
|
if (wy > 3)
|
| 328 |
|
|
wy += 2;
|
| 329 |
|
|
wy++;
|
| 330 |
|
|
|
| 331 |
|
|
if (c >= 12)
|
| 332 |
|
|
ra = c - 12;
|
| 333 |
|
|
else
|
| 334 |
|
|
ra = c + 32;
|
| 335 |
|
|
|
| 336 |
|
|
bool done = false;
|
| 337 |
|
|
char str[16];
|
| 338 |
|
|
int pos = 0; str[pos] = '\0';
|
| 339 |
|
|
while(!done) {
|
| 340 |
|
|
int chv = getch();
|
| 341 |
|
|
switch(chv) {
|
| 342 |
|
|
case KEY_ESCAPE:
|
| 343 |
|
|
pos = 0; str[pos] = '\0'; done = true;
|
| 344 |
|
|
break;
|
| 345 |
|
|
case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
|
| 346 |
|
|
done = true;
|
| 347 |
|
|
break;
|
| 348 |
|
|
case KEY_LEFT: case KEY_BACKSPACE:
|
| 349 |
|
|
if (pos > 0) pos--;
|
| 350 |
|
|
break;
|
| 351 |
|
|
case KEY_CLEAR:
|
| 352 |
|
|
pos = 0;
|
| 353 |
|
|
break;
|
| 354 |
|
|
case '0': case ' ': str[pos++] = '0'; break;
|
| 355 |
|
|
case '1': str[pos++] = '1'; break;
|
| 356 |
|
|
case '2': str[pos++] = '2'; break;
|
| 357 |
|
|
case '3': str[pos++] = '3'; break;
|
| 358 |
|
|
case '4': str[pos++] = '4'; break;
|
| 359 |
|
|
case '5': str[pos++] = '5'; break;
|
| 360 |
|
|
case '6': str[pos++] = '6'; break;
|
| 361 |
|
|
case '7': str[pos++] = '7'; break;
|
| 362 |
|
|
case '8': str[pos++] = '8'; break;
|
| 363 |
|
|
case '9': str[pos++] = '9'; break;
|
| 364 |
|
|
case 'A': case 'a': str[pos++] = 'A'; break;
|
| 365 |
|
|
case 'B': case 'b': str[pos++] = 'B'; break;
|
| 366 |
|
|
case 'C': case 'c': str[pos++] = 'C'; break;
|
| 367 |
|
|
case 'D': case 'd': str[pos++] = 'D'; break;
|
| 368 |
|
|
case 'E': case 'e': str[pos++] = 'E'; break;
|
| 369 |
|
|
case 'F': case 'f': str[pos++] = 'F'; break;
|
| 370 |
|
|
}
|
| 371 |
|
|
|
| 372 |
|
|
if (pos > 8)
|
| 373 |
|
|
pos = 8;
|
| 374 |
|
|
str[pos] = '\0';
|
| 375 |
|
|
|
| 376 |
|
|
attron(A_NORMAL | A_UNDERLINE);
|
| 377 |
|
|
mvprintw(wy, wx, "%-8s", str);
|
| 378 |
|
|
if (pos > 0) {
|
| 379 |
|
|
attron(A_NORMAL | A_UNDERLINE | A_BLINK);
|
| 380 |
|
|
mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
|
| 381 |
|
|
}
|
| 382 |
|
|
attrset(A_NORMAL);
|
| 383 |
|
|
}
|
| 384 |
|
|
|
| 385 |
|
|
if (pos > 0) {
|
| 386 |
|
|
int v;
|
| 387 |
|
|
v = strtoul(str, NULL, 16);
|
| 388 |
|
|
zip->cmd_write(ra, v);
|
| 389 |
|
|
}
|
| 390 |
|
|
}
|
| 391 |
|
|
|
| 392 |
|
|
void on_sigint(int v) {
|
| 393 |
|
|
endwin();
|
| 394 |
|
|
|
| 395 |
|
|
fprintf(stderr, "Interrupted!\n");
|
| 396 |
|
|
exit(-2);
|
| 397 |
|
|
}
|
| 398 |
|
|
|
| 399 |
|
|
int main(int argc, char **argv) {
|
| 400 |
|
|
// FPGAOPEN(m_fpga);
|
| 401 |
|
|
ZIPPY *zip; //
|
| 402 |
|
|
|
| 403 |
|
|
int skp=0, port = FPGAPORT;
|
| 404 |
|
|
bool use_usb = true;
|
| 405 |
|
|
|
| 406 |
|
|
skp=1;
|
| 407 |
|
|
for(int argn=0; argn<argc-skp; argn++) {
|
| 408 |
|
|
if (argv[argn+skp][0] == '-') {
|
| 409 |
|
|
if (argv[argn+skp][1] == 'u')
|
| 410 |
|
|
use_usb = true;
|
| 411 |
|
|
else if (argv[argn+skp][1] == 'p') {
|
| 412 |
|
|
use_usb = false;
|
| 413 |
|
|
if (isdigit(argv[argn+skp][2]))
|
| 414 |
|
|
port = atoi(&argv[argn+skp][2]);
|
| 415 |
|
|
}
|
| 416 |
|
|
skp++; argn--;
|
| 417 |
|
|
} else
|
| 418 |
|
|
argv[argn] = argv[argn+skp];
|
| 419 |
|
|
} argc -= skp;
|
| 420 |
|
|
|
| 421 |
|
|
if (use_usb)
|
| 422 |
|
|
m_fpga = new FPGA(new USBI());
|
| 423 |
|
|
else
|
| 424 |
|
|
m_fpga = new FPGA(new NETCOMMS(FPGAHOST, port));
|
| 425 |
|
|
zip = new ZIPPY(m_fpga);
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
initscr();
|
| 429 |
|
|
raw();
|
| 430 |
|
|
noecho();
|
| 431 |
|
|
keypad(stdscr, true);
|
| 432 |
|
|
|
| 433 |
|
|
signal(SIGINT, on_sigint);
|
| 434 |
|
|
|
| 435 |
|
|
int chv;
|
| 436 |
|
|
bool done = false;
|
| 437 |
|
|
|
| 438 |
|
|
zip->halt();
|
| 439 |
|
|
for(int i=0; (i<5)&&(zip->stalled()); i++)
|
| 440 |
|
|
;
|
| 441 |
|
|
if (!zip->stalled())
|
| 442 |
|
|
zip->read_state();
|
| 443 |
|
|
while((!done)&&(!gbl_err)) {
|
| 444 |
|
|
chv = getch();
|
| 445 |
|
|
switch(chv) {
|
| 446 |
|
|
case 'g': case 'G':
|
| 447 |
|
|
m_fpga->writeio(R_ZIPCTRL, CPU_GO);
|
| 448 |
|
|
// We just released the CPU, so we're now done.
|
| 449 |
|
|
done = true;
|
| 450 |
|
|
break;
|
| 451 |
|
|
case 'l': case 'L': case CTRL('L'):
|
| 452 |
|
|
redrawwin(stdscr);
|
| 453 |
|
|
break;
|
| 454 |
|
|
case 'q': case 'Q': case CTRL('C'):
|
| 455 |
|
|
case KEY_CANCEL: case KEY_CLOSE: case KEY_EXIT:
|
| 456 |
|
|
case KEY_ESCAPE:
|
| 457 |
|
|
done = true;
|
| 458 |
|
|
break;
|
| 459 |
|
|
case 'r': case 'R':
|
| 460 |
|
|
zip->reset();
|
| 461 |
|
|
erase();
|
| 462 |
|
|
break;
|
| 463 |
|
|
case 's': case 'S':
|
| 464 |
|
|
zip->step();
|
| 465 |
|
|
zip->read_state();
|
| 466 |
|
|
break;
|
| 467 |
|
|
case KEY_IC: case KEY_ENTER:
|
| 468 |
|
|
get_value(zip);
|
| 469 |
|
|
break;
|
| 470 |
|
|
case KEY_UP:
|
| 471 |
|
|
zip->cursor_up();
|
| 472 |
|
|
break;
|
| 473 |
|
|
case KEY_DOWN:
|
| 474 |
|
|
zip->cursor_down();
|
| 475 |
|
|
break;
|
| 476 |
|
|
case KEY_LEFT:
|
| 477 |
|
|
zip->cursor_left();
|
| 478 |
|
|
break;
|
| 479 |
|
|
case KEY_RIGHT:
|
| 480 |
|
|
zip->cursor_right();
|
| 481 |
|
|
break;
|
| 482 |
|
|
case ERR: case KEY_CLEAR:
|
| 483 |
|
|
default:
|
| 484 |
|
|
;
|
| 485 |
|
|
}
|
| 486 |
|
|
|
| 487 |
|
|
if ((!done)&&(!gbl_err)) {
|
| 488 |
|
|
if (zip->stalled())
|
| 489 |
|
|
erase();
|
| 490 |
|
|
}
|
| 491 |
|
|
}
|
| 492 |
|
|
|
| 493 |
|
|
endwin();
|
| 494 |
|
|
|
| 495 |
|
|
if (gbl_err) {
|
| 496 |
|
|
printf("Killed on error: could not access bus!\n");
|
| 497 |
|
|
exit(-2);
|
| 498 |
|
|
}
|
| 499 |
|
|
}
|
| 500 |
|
|
|
