URL
https://opencores.org/ocsvn/y80e/y80e/trunk
[/] [y80e/] [trunk/] [rtl/] [hierarchy.v] - Blame information for rev 2
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
bsa |
/*******************************************************************************************/
|
| 2 |
|
|
/** **/
|
| 3 |
|
|
/** COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
|
| 4 |
|
|
/** **/
|
| 5 |
|
|
/** chip design file include list Rev 0.0 07/17/2011 **/
|
| 6 |
|
|
/** **/
|
| 7 |
|
|
/*******************************************************************************************/
|
| 8 |
|
|
`include "defines.v" /* control signal mnemonics */
|
| 9 |
|
|
`include "control.v" /* processor control */
|
| 10 |
|
|
`include "datapath.v" /* processor data path */
|
| 11 |
|
|
`include "alu_log.v" /* alu logic unit */
|
| 12 |
|
|
`include "alu_math.v" /* alu math unit */
|
| 13 |
|
|
`include "alu_shft.v" /* alu shifter unit */
|
| 14 |
|
|
`include "aluamux.v" /* alu a input multiplexer */
|
| 15 |
|
|
`include "alubmux.v" /* alu b input multiplexer */
|
| 16 |
|
|
`include "aluout.v" /* alu output multiplexer */
|
| 17 |
|
|
`include "extint.v" /* processor external interface */
|
| 18 |
|
|
`include "machine.v" /* processor state machine */
|
| 19 |
|
|
`include "y80_top.v" /* cpu top level */
|
| 20 |
|
|
|
| 21 |
|
|
|
| 22 |
|
|
|
| 23 |
|
|
|
| 24 |
|
|
|
| 25 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.