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sandroamt |
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---- ----
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---- This file is part of the yaVGA project ----
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---- http://www.opencores.org/?do=project&who=yavga ----
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---- ----
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---- Description ----
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---- Implementation of yaVGA IP core ----
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---- ----
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---- To Do: ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Sandro Amato, sdroamt@netscape.net ----
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---- ----
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (c) 2009, Sandro Amato ----
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---- All rights reserved. ----
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---- ----
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---- Redistribution and use in source and binary forms, with or without ----
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---- modification, are permitted provided that the following conditions ----
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---- are met: ----
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---- ----
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---- * Redistributions of source code must retain the above ----
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---- copyright notice, this list of conditions and the ----
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---- following disclaimer. ----
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---- * Redistributions in binary form must reproduce the above ----
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---- copyright notice, this list of conditions and the ----
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---- following disclaimer in the documentation and/or other ----
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---- materials provided with the distribution. ----
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---- * Neither the name of SANDRO AMATO nor the names of its ----
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---- contributors may be used to endorse or promote products ----
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---- derived from this software without specific prior written ----
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---- permission. ----
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---- ----
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---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
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---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
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---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
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---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
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---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
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---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
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---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
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---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
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---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use work.yavga_pkg.all;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity charmaps_ROM is
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port (
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i_EN : in std_logic; -- RAM Enable Input
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i_clock : in std_logic; -- Clock
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i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 11-bit Address Input
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o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8-bit Data Output
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);
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end charmaps_ROM;
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architecture Behavioral of charmaps_ROM is
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signal s_EN : std_logic;
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constant c_rom_size : natural := 2**c_INTCHMAP_ADDR_BUS_W;
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type t_rom is array (c_rom_size-1 downto 0) of
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std_logic_vector (c_INTCHMAP_DATA_BUS_W - 1 downto 0);
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constant c_rom : t_rom := (
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-- AUTOMATICALLY GENERATED... START
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