URL https://opencores.org/ocsvn/yavga/yavga/trunk

Subversion Repositories yavga

[/] [yavga/] [trunk/] [vhdl/] [chars_RAM.vhd] - Blame information for rev 37

Details | Compare with Previous | View Log


--------------------------------------------------------------------------------
----                                                                        ----
---- This file is part of the yaVGA project                                 ----
---- http://www.opencores.org/?do=project&who=yavga                         ----
----                                                                        ----
---- Description                                                            ----
---- Implementation of yaVGA IP core                                        ----
----                                                                        ----
---- To Do:                                                                 ----
----                                                                        ----
----                                                                        ----
---- Author(s):                                                             ----
---- Sandro Amato, sdroamt@netscape.net                                     ----
----                                                                        ----
--------------------------------------------------------------------------------
----                                                                        ----
---- Copyright (c) 2009, Sandro Amato                                       ----
---- All rights reserved.                                                   ----
----                                                                        ----
---- Redistribution  and  use in  source  and binary forms, with or without ----
---- modification,  are  permitted  provided that  the following conditions ----
---- are met:                                                               ----
----                                                                        ----
----     * Redistributions  of  source  code  must  retain the above        ----
----       copyright   notice,  this  list  of  conditions  and  the        ----
----       following disclaimer.                                            ----
----     * Redistributions  in  binary form must reproduce the above        ----
----       copyright   notice,  this  list  of  conditions  and  the        ----
----       following  disclaimer in  the documentation and/or  other        ----
----       materials provided with the distribution.                        ----
----     * Neither  the  name  of  SANDRO AMATO nor the names of its        ----
----       contributors may be used to  endorse or  promote products        ----
----       derived from this software without specific prior written        ----
----       permission.                                                      ----
----                                                                        ----
---- THIS SOFTWARE IS PROVIDED  BY THE COPYRIGHT  HOLDERS AND  CONTRIBUTORS ----
---- "AS IS"  AND  ANY EXPRESS OR  IMPLIED  WARRANTIES, INCLUDING,  BUT NOT ----
---- LIMITED  TO, THE  IMPLIED  WARRANTIES  OF MERCHANTABILITY  AND FITNESS ----
---- FOR  A PARTICULAR  PURPOSE  ARE  DISCLAIMED. IN  NO  EVENT  SHALL  THE ----
---- COPYRIGHT  OWNER  OR CONTRIBUTORS  BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL,  SPECIAL,  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
---- BUT  NOT LIMITED  TO,  PROCUREMENT OF  SUBSTITUTE  GOODS  OR SERVICES; ----
---- LOSS  OF  USE,  DATA,  OR PROFITS;  OR  BUSINESS INTERRUPTION) HOWEVER ----
---- CAUSED  AND  ON  ANY THEORY  OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
---- LIABILITY,  OR  TORT  (INCLUDING  NEGLIGENCE  OR OTHERWISE) ARISING IN ----
---- ANY  WAY OUT  OF THE  USE  OF  THIS  SOFTWARE,  EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE.                                            ----
--------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
use work.yavga_pkg.all;
 
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity chars_RAM is
  port (
    i_clock_rw : in  std_logic;         -- Write Clock
    i_EN_rw    : in  std_logic;         -- Write RAM Enable Input
    i_WE_rw    : in  std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);  -- Write Enable Input
    i_ADDR_rw  : in  std_logic_vector(10 downto 0);  -- Write 11-bit Address Input
    i_DI_rw    : in  std_logic_vector(31 downto 0);  -- Write 32-bit Data Input
    o_DI_rw    : out std_logic_vector(31 downto 0);  -- Write 32-bit Data Input
 
    i_SSR : in std_logic;               -- Synchronous Set/Reset Input
 
    i_clock_r : in  std_logic;          -- Read Clock
    i_EN_r    : in  std_logic;
    i_ADDR_r  : in  std_logic_vector(12 downto 0);  -- Read 13-bit Address Input
    o_DO_r    : out std_logic_vector(7 downto 0)    -- Read 8-bit Data Output
    );
end chars_RAM;
 
architecture Behavioral of chars_RAM is
  signal s0_DO_r : std_logic_vector(7 downto 0);
  signal s1_DO_r : std_logic_vector(7 downto 0);
  signal s2_DO_r : std_logic_vector(7 downto 0);
  signal s3_DO_r : std_logic_vector(7 downto 0);
 
  constant c_ram_size : natural := 2**(c_CHR_ADDR_BUS_W);
 
  type t_ram is array (c_ram_size-1 downto 0) of
    std_logic_vector (c_INTCHR_DATA_BUS_W - 1 downto 0);
 
  shared variable v_ram0 : t_ram := (
    27 => X"05",  -- config "bg and curs color" (108/4 = 27)
 
    768    => X"00", 769 => X"04", 770 => X"08", 771 => X"0C",
    772    => X"10", 773 => X"14", 774 => X"18", 775 => X"1C",
    1024   => X"20", 1025 => X"24", 1026 => X"28", 1027 => X"2C",
    1028   => X"30", 1029 => X"34", 1030 => X"38", 1031 => X"3C",
    1032   => X"40", 1033 => X"44", 1034 => X"48", 1035 => X"4C",
    1036   => X"50", 1037 => X"54", 1038 => X"58", 1039 => X"5C",
    1040   => X"60", 1041 => X"64", 1042 => X"68", 1043 => X"6C",
    1044   => X"70", 1045 => X"74", 1046 => X"78", 1047 => X"7C",
    1126   => X"53",                    -- S
    1127   => X"72",                    -- r
    1128   => X"6D",                    -- m
    1129   => X"20",                    --  
    1130   => X"64",                    -- d
    1131   => X"6D",                    -- m
    1132   => X"65",                    -- e
    1133   => X"61",                    -- a
    1134   => X"6E",                    -- n
    others => X"00"
    );
 
  shared variable v_ram1 : t_ram := (
    27 => X"07",  -- config "xy coords spans on three bytes" (108/4 = 27)
 
    768    => X"01", 769 => X"05", 770 => X"09", 771 => X"0D",
    772    => X"11", 773 => X"15", 774 => X"19", 775 => X"1D",
    1024   => X"21", 1025 => X"25", 1026 => X"29", 1027 => X"2D",
    1028   => X"31", 1029 => X"35", 1030 => X"39", 1031 => X"3D",
    1032   => X"41", 1033 => X"45", 1034 => X"49", 1035 => X"4D",
    1036   => X"51", 1037 => X"55", 1038 => X"59", 1039 => X"5D",
    1040   => X"61", 1041 => X"65", 1042 => X"69", 1043 => X"6D",
    1044   => X"71", 1045 => X"75", 1046 => X"79", 1047 => X"7D",
    1126   => X"61",                    -- a
    1127   => X"6F",                    -- o
    1128   => X"61",                    -- a
    1129   => X"2D",                    -- -
    1130   => X"72",                    -- r
    1131   => X"74",                    -- t
    1132   => X"74",                    -- t
    1133   => X"70",                    -- p
    1134   => X"65",                    -- e
    others => X"00"
    );
 
  shared variable v_ram2 : t_ram := (
    27 => X"09",  -- config "xy coords spans on three bytes" (108/4 = 27)
 
    768    => X"02", 769 => X"06", 770 => X"0A", 771 => X"0E",
    772    => X"12", 773 => X"16", 774 => X"1A", 775 => X"1E",
    1024   => X"22", 1025 => X"26", 1026 => X"2A", 1027 => X"2E",
    1028   => X"32", 1029 => X"36", 1030 => X"3A", 1031 => X"3E",
    1032   => X"42", 1033 => X"46", 1034 => X"4A", 1035 => X"4E",
    1036   => X"52", 1037 => X"56", 1038 => X"5A", 1039 => X"5E",
    1040   => X"62", 1041 => X"66", 1042 => X"6A", 1043 => X"6E",
    1044   => X"72", 1045 => X"76", 1046 => X"7A", 1047 => X"7E",
    1126   => X"6E",                    -- n
    1127   => X"20",                    --  
    1128   => X"74",                    -- t
    1129   => X"20",                    --  
    1130   => X"6F",                    -- o
    1131   => X"40",                    -- @
    1132   => X"73",                    -- s
    1133   => X"65",                    -- e
    1134   => X"74",                    -- t
    others => X"00"
    );
 
  shared variable v_ram3 : t_ram := (
    27 => X"5E",  -- config "xy coords spans on three bytes" (108/4 = 27)
 
    768    => X"03", 769 => X"07", 770 => X"0B", 771 => X"0F",
    772    => X"13", 773 => X"17", 774 => X"1B", 775 => X"1F",
    1024   => X"23", 1025 => X"27", 1026 => X"2B", 1027 => X"2F",
    1028   => X"33", 1029 => X"37", 1030 => X"3B", 1031 => X"3F",
    1032   => X"43", 1033 => X"47", 1034 => X"4B", 1035 => X"4F",
    1036   => X"53", 1037 => X"57", 1038 => X"5B", 1039 => X"5F",
    1040   => X"63", 1041 => X"67", 1042 => X"6B", 1043 => X"6F",
    1044   => X"73", 1045 => X"77", 1046 => X"7B", 1047 => X"7F",
    1126   => X"64",                    -- d
    1127   => X"41",                    -- A
    1128   => X"6F",                    -- o
    1129   => X"73",                    -- s
    1130   => X"61",                    -- a
    1131   => X"6E",                    -- n
    1132   => X"63",                    -- c
    1133   => X"2E",                    -- .
    1134   => X"20",                    --  
    others => X"00"
    );
 
begin
 
  p_rw0_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(31 downto 24) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(31 downto 24) <= v_ram0(conv_integer(i_ADDR_rw));
        if (i_WE_rw(0) = '1') then
          v_ram0(conv_integer(i_ADDR_rw)) := i_DI_rw(31 downto 24);
        end if;
      end if;
    end if;
  end process;
 
  p_rw1_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(23 downto 16) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(23 downto 16) <= v_ram1(conv_integer(i_ADDR_rw));
        if (i_WE_rw(1) = '1') then
          v_ram1(conv_integer(i_ADDR_rw)) := i_DI_rw(23 downto 16);
        end if;
      end if;
    end if;
  end process;
 
  p_rw2_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(15 downto 8) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(15 downto 8) <= v_ram2(conv_integer(i_ADDR_rw));
        if (i_WE_rw(2) = '1') then
          v_ram2(conv_integer(i_ADDR_rw)) := i_DI_rw(15 downto 8);
        end if;
      end if;
    end if;
  end process;
 
  p_rw3_port : process (i_clock_rw)
  begin
    if rising_edge(i_clock_rw) then
      if i_SSR = '1' then
        o_DI_rw(7 downto 0) <= (others => '0');
      elsif (i_EN_rw = '1') then
        o_DI_rw(7 downto 0) <= v_ram3(conv_integer(i_ADDR_rw));
        if (i_WE_rw(3) = '1') then
          v_ram3(conv_integer(i_ADDR_rw)) := i_DI_rw(7 downto 0);
        end if;
      end if;
    end if;
  end process;
 
 
  p_ro0_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s0_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s0_DO_r <= v_ram0(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  p_ro1_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s1_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s1_DO_r <= v_ram1(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  p_ro2_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s2_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s2_DO_r <= v_ram2(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  p_ro3_port : process (i_clock_r)
  begin
    if rising_edge(i_clock_r) then
      if i_SSR = '1' then
        s3_DO_r <= (others => '0');
      elsif (i_EN_r = '1') then
        s3_DO_r <= v_ram3(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));
      end if;
    end if;
  end process;
 
  o_DO_r <=
    s0_DO_r when i_ADDR_r(1 downto 0) = "00" else
    s1_DO_r when i_ADDR_r(1 downto 0) = "01" else
    s2_DO_r when i_ADDR_r(1 downto 0) = "10" else
    s3_DO_r when i_ADDR_r(1 downto 0) = "11" else
    (others => 'X');
end Behavioral;

Line No.	Rev	Author	Line
1	2	sandroamt	`--------------------------------------------------------------------------------`
2			`---- ----`
3			`---- This file is part of the yaVGA project ----`
4			`---- http://www.opencores.org/?do=project&who=yavga ----`
5			`---- ----`
6			`---- Description ----`
7			`---- Implementation of yaVGA IP core ----`
8			`---- ----`
9			`---- To Do: ----`
10			`---- ----`
11			`---- ----`
12			`---- Author(s): ----`
13			`---- Sandro Amato, sdroamt@netscape.net ----`
14			`---- ----`
15			`--------------------------------------------------------------------------------`
16			`---- ----`
17			`---- Copyright (c) 2009, Sandro Amato ----`
18			`---- All rights reserved. ----`
19			`---- ----`
20			`---- Redistribution and use in source and binary forms, with or without ----`
21			`---- modification, are permitted provided that the following conditions ----`
22			`---- are met: ----`
23			`---- ----`
24			`---- * Redistributions of source code must retain the above ----`
25			`---- copyright notice, this list of conditions and the ----`
26			`---- following disclaimer. ----`
27			`---- * Redistributions in binary form must reproduce the above ----`
28			`---- copyright notice, this list of conditions and the ----`
29			`---- following disclaimer in the documentation and/or other ----`
30			`---- materials provided with the distribution. ----`
31			`---- * Neither the name of SANDRO AMATO nor the names of its ----`
32			`---- contributors may be used to endorse or promote products ----`
33			`---- derived from this software without specific prior written ----`
34			`---- permission. ----`
35			`---- ----`
36			`---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----`
37			`---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----`
38			`---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
39			`---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----`
40			`---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
41			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----`
42			`---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----`
43			`---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----`
44			`---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----`
45			`---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----`
46			`---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
47			`---- POSSIBILITY OF SUCH DAMAGE. ----`
48			`--------------------------------------------------------------------------------`
49
50
51			`library IEEE;`
52			`use IEEE.STD_LOGIC_1164.all;`
53			`use IEEE.STD_LOGIC_ARITH.all;`
54			`use IEEE.STD_LOGIC_UNSIGNED.all;`
55
56	28	sandroamt	`use work.yavga_pkg.all;`
57
58	2	sandroamt	`-- Uncomment the following lines to use the declarations that are`
59			`-- provided for instantiating Xilinx primitive components.`
60	36	sandroamt	`--library UNISIM;`
61			`--use UNISIM.VComponents.all;`
62	2	sandroamt
63			`entity chars_RAM is`
64			`port (`
65			`i_clock_rw : in std_logic; -- Write Clock`
66			`i_EN_rw : in std_logic; -- Write RAM Enable Input`
67	28	sandroamt	`i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0); -- Write Enable Input`
68	2	sandroamt	`i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input`
69			`i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input`
70			`o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input`
71
72			`i_SSR : in std_logic; -- Synchronous Set/Reset Input`
73
74			`i_clock_r : in std_logic; -- Read Clock`
75	23	sandroamt	`i_EN_r : in std_logic;`
76	2	sandroamt	`i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input`
77			`o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output`
78			`);`
79			`end chars_RAM;`
80
81	36	sandroamt	`architecture Behavioral of chars_RAM is`
82	2	sandroamt	`signal s0_DO_r : std_logic_vector(7 downto 0);`
83			`signal s1_DO_r : std_logic_vector(7 downto 0);`
84			`signal s2_DO_r : std_logic_vector(7 downto 0);`
85			`signal s3_DO_r : std_logic_vector(7 downto 0);`
86
87	36	sandroamt	`constant c_ram_size : natural := 2**(c_CHR_ADDR_BUS_W);`
88
89			`type t_ram is array (c_ram_size-1 downto 0) of`
90			`std_logic_vector (c_INTCHR_DATA_BUS_W - 1 downto 0);`
91
92			`shared variable v_ram0 : t_ram := (`
93	37	sandroamt	`27 => X"05", -- config "bg and curs color" (108/4 = 27)`
94
95			`768 => X"00", 769 => X"04", 770 => X"08", 771 => X"0C",`
96			`772 => X"10", 773 => X"14", 774 => X"18", 775 => X"1C",`
97			`1024 => X"20", 1025 => X"24", 1026 => X"28", 1027 => X"2C",`
98			`1028 => X"30", 1029 => X"34", 1030 => X"38", 1031 => X"3C",`
99			`1032 => X"40", 1033 => X"44", 1034 => X"48", 1035 => X"4C",`
100			`1036 => X"50", 1037 => X"54", 1038 => X"58", 1039 => X"5C",`
101			`1040 => X"60", 1041 => X"64", 1042 => X"68", 1043 => X"6C",`
102			`1044 => X"70", 1045 => X"74", 1046 => X"78", 1047 => X"7C",`
103	36	sandroamt	`1126 => X"53", -- S`
104			`1127 => X"72", -- r`
105			`1128 => X"6D", -- m`
106			`1129 => X"20", --`
107			`1130 => X"64", -- d`
108			`1131 => X"6D", -- m`
109			`1132 => X"65", -- e`
110			`1133 => X"61", -- a`
111			`1134 => X"6E", -- n`
112			`others => X"00"`
113			`);`
114
115			`shared variable v_ram1 : t_ram := (`
116	37	sandroamt	`27 => X"07", -- config "xy coords spans on three bytes" (108/4 = 27)`
117
118			`768 => X"01", 769 => X"05", 770 => X"09", 771 => X"0D",`
119			`772 => X"11", 773 => X"15", 774 => X"19", 775 => X"1D",`
120			`1024 => X"21", 1025 => X"25", 1026 => X"29", 1027 => X"2D",`
121			`1028 => X"31", 1029 => X"35", 1030 => X"39", 1031 => X"3D",`
122			`1032 => X"41", 1033 => X"45", 1034 => X"49", 1035 => X"4D",`
123			`1036 => X"51", 1037 => X"55", 1038 => X"59", 1039 => X"5D",`
124			`1040 => X"61", 1041 => X"65", 1042 => X"69", 1043 => X"6D",`
125			`1044 => X"71", 1045 => X"75", 1046 => X"79", 1047 => X"7D",`
126	36	sandroamt	`1126 => X"61", -- a`
127			`1127 => X"6F", -- o`
128			`1128 => X"61", -- a`
129			`1129 => X"2D", -- -`
130			`1130 => X"72", -- r`
131			`1131 => X"74", -- t`
132			`1132 => X"74", -- t`
133			`1133 => X"70", -- p`
134			`1134 => X"65", -- e`
135			`others => X"00"`
136			`);`
137
138			`shared variable v_ram2 : t_ram := (`
139	37	sandroamt	`27 => X"09", -- config "xy coords spans on three bytes" (108/4 = 27)`
140
141			`768 => X"02", 769 => X"06", 770 => X"0A", 771 => X"0E",`
142			`772 => X"12", 773 => X"16", 774 => X"1A", 775 => X"1E",`
143			`1024 => X"22", 1025 => X"26", 1026 => X"2A", 1027 => X"2E",`
144			`1028 => X"32", 1029 => X"36", 1030 => X"3A", 1031 => X"3E",`
145			`1032 => X"42", 1033 => X"46", 1034 => X"4A", 1035 => X"4E",`
146			`1036 => X"52", 1037 => X"56", 1038 => X"5A", 1039 => X"5E",`
147			`1040 => X"62", 1041 => X"66", 1042 => X"6A", 1043 => X"6E",`
148			`1044 => X"72", 1045 => X"76", 1046 => X"7A", 1047 => X"7E",`
149	36	sandroamt	`1126 => X"6E", -- n`
150			`1127 => X"20", --`
151			`1128 => X"74", -- t`
152			`1129 => X"20", --`
153			`1130 => X"6F", -- o`
154			`1131 => X"40", -- @`
155			`1132 => X"73", -- s`
156			`1133 => X"65", -- e`
157			`1134 => X"74", -- t`
158			`others => X"00"`
159			`);`
160
161			`shared variable v_ram3 : t_ram := (`
162	37	sandroamt	`27 => X"5E", -- config "xy coords spans on three bytes" (108/4 = 27)`
163
164			`768 => X"03", 769 => X"07", 770 => X"0B", 771 => X"0F",`
165			`772 => X"13", 773 => X"17", 774 => X"1B", 775 => X"1F",`
166			`1024 => X"23", 1025 => X"27", 1026 => X"2B", 1027 => X"2F",`
167			`1028 => X"33", 1029 => X"37", 1030 => X"3B", 1031 => X"3F",`
168			`1032 => X"43", 1033 => X"47", 1034 => X"4B", 1035 => X"4F",`
169			`1036 => X"53", 1037 => X"57", 1038 => X"5B", 1039 => X"5F",`
170			`1040 => X"63", 1041 => X"67", 1042 => X"6B", 1043 => X"6F",`
171			`1044 => X"73", 1045 => X"77", 1046 => X"7B", 1047 => X"7F",`
172	36	sandroamt	`1126 => X"64", -- d`
173			`1127 => X"41", -- A`
174			`1128 => X"6F", -- o`
175			`1129 => X"73", -- s`
176			`1130 => X"61", -- a`
177			`1131 => X"6E", -- n`
178			`1132 => X"63", -- c`
179			`1133 => X"2E", -- .`
180			`1134 => X"20", --`
181			`others => X"00"`
182			`);`
183
184	2	sandroamt	`begin`
185
186	36	sandroamt	`p_rw0_port : process (i_clock_rw)`
187			`begin`
188			`if rising_edge(i_clock_rw) then`
189			`if i_SSR = '1' then`
190			`o_DI_rw(31 downto 24) <= (others => '0');`
191			`elsif (i_EN_rw = '1') then`
192			`o_DI_rw(31 downto 24) <= v_ram0(conv_integer(i_ADDR_rw));`
193			`if (i_WE_rw(0) = '1') then`
194			`v_ram0(conv_integer(i_ADDR_rw)) := i_DI_rw(31 downto 24);`
195			`end if;`
196			`end if;`
197			`end if;`
198			`end process;`
199	2	sandroamt
200	36	sandroamt	`p_rw1_port : process (i_clock_rw)`
201			`begin`
202			`if rising_edge(i_clock_rw) then`
203			`if i_SSR = '1' then`
204			`o_DI_rw(23 downto 16) <= (others => '0');`
205			`elsif (i_EN_rw = '1') then`
206			`o_DI_rw(23 downto 16) <= v_ram1(conv_integer(i_ADDR_rw));`
207			`if (i_WE_rw(1) = '1') then`
208			`v_ram1(conv_integer(i_ADDR_rw)) := i_DI_rw(23 downto 16);`
209			`end if;`
210			`end if;`
211			`end if;`
212			`end process;`
213	2	sandroamt
214	36	sandroamt	`p_rw2_port : process (i_clock_rw)`
215			`begin`
216			`if rising_edge(i_clock_rw) then`
217			`if i_SSR = '1' then`
218			`o_DI_rw(15 downto 8) <= (others => '0');`
219			`elsif (i_EN_rw = '1') then`
220			`o_DI_rw(15 downto 8) <= v_ram2(conv_integer(i_ADDR_rw));`
221			`if (i_WE_rw(2) = '1') then`
222			`v_ram2(conv_integer(i_ADDR_rw)) := i_DI_rw(15 downto 8);`
223			`end if;`
224			`end if;`
225			`end if;`
226			`end process;`
227	2	sandroamt
228	36	sandroamt	`p_rw3_port : process (i_clock_rw)`
229			`begin`
230			`if rising_edge(i_clock_rw) then`
231			`if i_SSR = '1' then`
232			`o_DI_rw(7 downto 0) <= (others => '0');`
233			`elsif (i_EN_rw = '1') then`
234			`o_DI_rw(7 downto 0) <= v_ram3(conv_integer(i_ADDR_rw));`
235			`if (i_WE_rw(3) = '1') then`
236			`v_ram3(conv_integer(i_ADDR_rw)) := i_DI_rw(7 downto 0);`
237			`end if;`
238			`end if;`
239			`end if;`
240			`end process;`
241	2	sandroamt
242
243	36	sandroamt	`p_ro0_port : process (i_clock_r)`
244			`begin`
245			`if rising_edge(i_clock_r) then`
246			`if i_SSR = '1' then`
247			`s0_DO_r <= (others => '0');`
248			`elsif (i_EN_r = '1') then`
249			`s0_DO_r <= v_ram0(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
250			`end if;`
251			`end if;`
252			`end process;`
253	2	sandroamt
254	36	sandroamt	`p_ro1_port : process (i_clock_r)`
255			`begin`
256			`if rising_edge(i_clock_r) then`
257			`if i_SSR = '1' then`
258			`s1_DO_r <= (others => '0');`
259			`elsif (i_EN_r = '1') then`
260			`s1_DO_r <= v_ram1(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
261			`end if;`
262			`end if;`
263			`end process;`
264	2	sandroamt
265	36	sandroamt	`p_ro2_port : process (i_clock_r)`
266			`begin`
267			`if rising_edge(i_clock_r) then`
268			`if i_SSR = '1' then`
269			`s2_DO_r <= (others => '0');`
270			`elsif (i_EN_r = '1') then`
271			`s2_DO_r <= v_ram2(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
272			`end if;`
273			`end if;`
274			`end process;`
275	2	sandroamt
276	36	sandroamt	`p_ro3_port : process (i_clock_r)`
277			`begin`
278			`if rising_edge(i_clock_r) then`
279			`if i_SSR = '1' then`
280			`s3_DO_r <= (others => '0');`
281			`elsif (i_EN_r = '1') then`
282			`s3_DO_r <= v_ram3(conv_integer(i_ADDR_r(i_ADDR_r'left downto 2)));`
283			`end if;`
284			`end if;`
285			`end process;`
286	2	sandroamt
287	36	sandroamt	`o_DO_r <=`
288			`s0_DO_r when i_ADDR_r(1 downto 0) = "00" else`
289			`s1_DO_r when i_ADDR_r(1 downto 0) = "01" else`
290			`s2_DO_r when i_ADDR_r(1 downto 0) = "10" else`
291			`s3_DO_r when i_ADDR_r(1 downto 0) = "11" else`
292			`(others => 'X');`
293			`end Behavioral;`

Browse

Tools

Subversion Repositories yavga

[/] [yavga/] [trunk/] [vhdl/] [chars_RAM.vhd] - Blame information for rev 37