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sandroamt |
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---- ----
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---- This file is part of the yaVGA project ----
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---- http://www.opencores.org/?do=project&who=yavga ----
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---- ----
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---- Description ----
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---- Implementation of yaVGA IP core ----
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---- ----
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---- To Do: ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Sandro Amato, sdroamt@netscape.net ----
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---- ----
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--------------------------------------------------------------------------------
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---- ----
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---- Copyright (c) 2009, Sandro Amato ----
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---- All rights reserved. ----
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---- ----
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---- Redistribution and use in source and binary forms, with or without ----
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---- modification, are permitted provided that the following conditions ----
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---- are met: ----
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---- ----
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---- * Redistributions of source code must retain the above ----
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---- copyright notice, this list of conditions and the ----
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---- following disclaimer. ----
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---- * Redistributions in binary form must reproduce the above ----
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---- copyright notice, this list of conditions and the ----
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---- following disclaimer in the documentation and/or other ----
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---- materials provided with the distribution. ----
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---- * Neither the name of SANDRO AMATO nor the names of its ----
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---- contributors may be used to endorse or promote products ----
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---- derived from this software without specific prior written ----
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---- permission. ----
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---- ----
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---- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ----
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---- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ----
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---- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ----
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---- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ----
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---- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ----
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---- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ----
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---- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ----
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---- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ----
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---- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity waveform_RAM is
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port (
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i_DIA : in std_logic_vector(15 downto 0); -- 16-bit Data Input
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-- i_DIPA : in std_logic; -- 2-bit parity Input
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-- i_ENA : in std_logic; -- RAM Enable Input
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i_WEA : in std_logic; -- Write Enable Input
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-- i_SSRA : in std_logic; -- Synchronous Set/Reset Input
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i_clockA : in std_logic; -- Clock
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i_ADDRA : in std_logic_vector(9 downto 0); -- 10-bit Address Input
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--o_DOA : out std_logic_vector(15 downto 0); -- 16-bit Data Output
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-- o_DOPA : out std_logic -- 2-bit parity Output
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--
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i_DIB : in std_logic_vector(15 downto 0); -- 16-bit Data Input
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-- i_DIPB : in std_logic; -- 2-bit parity Input
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-- i_ENB : in std_logic; -- RAM Enable Input
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i_WEB : in std_logic; -- Write Enable Input
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-- i_SSRB : in std_logic; -- Synchronous Set/Reset Input
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i_clockB : in std_logic; -- Clock
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i_ADDRB : in std_logic_vector(9 downto 0); -- 10-bit Address Input
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o_DOB : out std_logic_vector(15 downto 0) -- 16-bit Data Output
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-- o_DOPB : out std_logic -- 2-bit parity Output
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);
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end waveform_RAM;
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architecture rtl of waveform_RAM is
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begin
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-- wave form or video-line memory
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-- |------| |-------------------------------------------|
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-- | P P | | D D D | D D D | D D D D D D D D D D |
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-- |======| |===========================================|
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-- |17 16 | | 15 14 13 | 12 11 10 | 9 8 7 6 5 4 3 2 1 0 |
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-- |======| |===========================================|
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-- | Free | | Reserv. | R G B | vert. pos. |
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-- |------| |-------------------------------------------|
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--
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Inst_waveform_RAM : RAMB16_S18_S18
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generic map (
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WRITE_MODE_A => "READ_FIRST", -- "WRITE_FIRST";
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INIT_A => B"000000000000000000",
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SRVAL_A => B"000000000000000000",
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--
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WRITE_MODE_B => "READ_FIRST", -- "WRITE_FIRST";
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INIT_B => B"000000000000000000",
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SRVAL_B => B"000000000000000000",
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--
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--INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_00 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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INIT_01 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_02 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_03 => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
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INIT_04 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_05 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_06 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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INIT_07 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
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--INIT_08 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
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INIT_08 => X"112A114011C211F4117C10FA110E112A112A112A112A112A112A112A112A192A",
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--INIT_09 => X"1129112911291129112911291129112911291129112911291129112911291129",
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INIT_09 => X"1129112911291129112911291129112911291129112911291129112911291529",
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INIT_0A => X"1128112811281128112811281128112811281128112811281128112811281128",
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INIT_0B => X"1127112711271127112711271127112711271127112711271127112711271127",
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INIT_0C => X"1126112611261126112611261126112611261126112611261126112611261126",
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INIT_0D => X"1125112511251125112511251125112511251125112511251125112511251125",
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INIT_0E => X"1124112411241124112411241124112411241124112411241124112411241124",
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INIT_0F => X"1123112311231123112311231123112311231123112311231123112311231123",
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--
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INIT_10 => X"1123112311231123112311231123112311231123112311231123112311231123",
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INIT_11 => X"1124112411241124112411241124112411241124112411241124112411241124",
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INIT_12 => X"1125112511251125112511251125112511251125112511251125112511251125",
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INIT_13 => X"1126112611261126112611261126112611261126112611261126112611261126",
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INIT_14 => X"1127112711271127112711271127112711271127112711271127112711271127",
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INIT_15 => X"1128112811281128112811281128112811281128112811281128112811281128",
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INIT_16 => X"1129112911291129112911291129112911291129112911291129112911291129",
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INIT_17 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
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INIT_18 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
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INIT_19 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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INIT_1A => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_1B => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_1C => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
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INIT_1D => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_1E => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_1F => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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--
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INIT_20 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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INIT_21 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_22 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_23 => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
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INIT_24 => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_25 => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_26 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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INIT_27 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
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INIT_28 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
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INIT_29 => X"1129112911291129112911291129112911291129112911291129112911291129",
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INIT_2A => X"1128112811281128112811281128112811281128112811281128112811281128",
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INIT_2B => X"1127112711271127112711271127112711271127112711271127112711271127",
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INIT_2C => X"1126112611261126112611261126112611261126112611261126112611261126",
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INIT_2D => X"1125112511251125112511251125112511251125112511251125112511251125",
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INIT_2E => X"1124112411241124112411241124112411241124112411241124112411241124",
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INIT_2F => X"1123112311231123112311231123112311231123112311231123112311231123",
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--
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INIT_30 => X"1123112311231123112311231123112311231123112311231123112311231123",
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INIT_31 => X"1124112411241124112411241124112411241124112411241124112411241124",
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INIT_32 => X"1125112511251125112511251125112511251125112511251125112511251125",
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INIT_33 => X"1126112611261126112611261126112611261126112611261126112611261126",
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INIT_34 => X"1127112711271127112711271127112711271127112711271127112711271127",
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INIT_35 => X"1128112811281128112811281128112811281128112811281128112811281128",
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INIT_36 => X"1129112911291129112911291129112911291129112911291129112911291129",
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INIT_37 => X"112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A112A",
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INIT_38 => X"112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B112B",
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INIT_39 => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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INIT_3A => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_3B => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_3C => X"112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F112F",
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INIT_3D => X"112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E112E",
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INIT_3E => X"112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D112D",
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INIT_3F => X"112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C112C",
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--
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INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
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)
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port map(
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DIA => i_DIA, -- 16 bit data Input
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DIPA => (others => '1'), -- 2 bit data parity Input
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ENA => '1', -- 1-bit RAM enable Input
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WEA => i_WEA, -- 1-bit Write Enable Input
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SSRA => '0', -- 1-bit Synchronous Set/Reset Input
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CLKA => i_clockA, -- 1-bit Clock Input
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ADDRA => i_ADDRA, -- 10-bit Address Input
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DOA => open, -- o_DOA, -- 16-bit Data Output
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DOPA => open, -- 2-bit Data Parity Output
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--
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DIB => i_DIB, -- 16 bit data Input
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DIPB => (others => '1'), -- 2 bit data parity Input
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ENB => '1', -- 1-bit RAM enable Input
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WEB => i_WEB, -- 1-bit Write Enable Input
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SSRB => '0', -- 1-bit Synchronous Set/Reset Input
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CLKB => i_clockB, -- 1-bit Clock Input
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ADDRB => i_ADDRB, -- 10-bit Address Input
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DOB => o_DOB, -- 16-bit Data Output
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DOPB => open -- 2-bit Data Parity Output
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| 210 |
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);
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| 212 |
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end rtl;
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