URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [risc_boot/] [risc_boot_tb.v] - Blame information for rev 22

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  User Risc Core Boot Validation                              ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////     1. User Risc core is booted using  compiled code of      ////
////        user_risc_boot.hex                                    ////
////     2. User Risc core uses Serial Flash and SDRAM to boot    ////
////     3. After successful boot, Risc core will  write signature////
////        in to  user register from 0x3000_0018 to 0x3000_002C  ////
////     4. Through the External Wishbone Interface we read back  ////
////         and validate the user register to declared pass fail ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision :                                                  ////
////    0.1 - 12th June 2021, Dinesh A                            ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`default_nettype none
 
`timescale 1 ns / 1 ps
 
`include "uprj_netlists.v"
`include "caravel_netlists.v"
`include "spiflash.v"
`include "mt48lc8m8a2.v"
 
module risc_boot_tb;
        reg clock;
        reg RSTB;
        reg CSB;
        reg power1, power2;
        reg power3, power4;
 
        wire gpio;
        wire [37:0] mprj_io;
        wire [7:0] mprj_io_0;
        wire [15:0] checkbits;
 
        assign checkbits = mprj_io[31:16];
 
        assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
 
        // External clock is used by default.  Make this artificially fast for the
        // simulation.  Normally this would be a slow clock and the digital PLL
        // would be the fast clock.
 
        always #12.5 clock <= (clock === 1'b0);
 
        initial begin
                clock = 0;
        end
 
        `ifdef WFDUMP
        initial
        begin
           $dumpfile("simx.vcd");
           $dumpvars(1,risc_boot_tb);
           //$dumpvars(2,risc_boot_tb.uut);
           $dumpvars(1,risc_boot_tb.uut.mprj.u_core);
           //$dumpvars(0,risc_boot_tb.u_user_spiflash);
           $display("Waveform Dump started");
        end
        `endif
 
        initial begin
 
                // Repeat cycles of 1000 clock edges as needed to complete testbench
                repeat (600) begin
                        repeat (1000) @(posedge clock);
                        // $display("+1000 cycles");
                end
                $display("%c[1;31m",27);
                `ifdef GL
                        $display ("Monitor: Timeout, Test user Risc Boot (GL) Failed");
                `else
                        $display ("Monitor: Timeout, Test user Risc Boot (RTL) Failed");
                `endif
                $display("%c[0m",27);
                $finish;
        end
 
        initial begin
           wait(checkbits == 16'h AB60);
                $display("Monitor: Test User Risc Boot Started");
                wait(checkbits == 16'h AB61);
                $display("#############################################");
                `ifdef GL
                $display("Monitor: Test User Risc Boot (GL) Passed");
                `else
                    $display("Monitor: Test User Risc Boot (RTL) Passed");
                `endif
                $display("#############################################");
            $finish;
        end
 
        initial begin
                RSTB <= 1'b0;
                CSB  <= 1'b1;           // Force CSB high
                #2000;
                RSTB <= 1'b1;           // Release reset
                #170000;
                CSB = 1'b0;             // CSB can be released
        end
 
        initial begin           // Power-up sequence
                power1 <= 1'b0;
                power2 <= 1'b0;
                power3 <= 1'b0;
                power4 <= 1'b0;
                #100;
                power1 <= 1'b1;
                #100;
                power2 <= 1'b1;
                #100;
                power3 <= 1'b1;
                #100;
                power4 <= 1'b1;
        end
 
        //always @(mprj_io) begin
        //      #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
        //end
 
        wire flash_csb;
        wire flash_clk;
        wire flash_io0;
        wire flash_io1;
 
        wire VDD3V3 = power1;
        wire VDD1V8 = power2;
        wire USER_VDD3V3 = power3;
        wire USER_VDD1V8 = power4;
        wire VSS = 1'b0;
 
        caravel uut (
                .vddio    (VDD3V3),
                .vssio    (VSS),
                .vdda     (VDD3V3),
                .vssa     (VSS),
                .vccd     (VDD1V8),
                .vssd     (VSS),
                .vdda1    (USER_VDD3V3),
                .vdda2    (USER_VDD3V3),
                .vssa1    (VSS),
                .vssa2    (VSS),
                .vccd1    (USER_VDD1V8),
                .vccd2    (USER_VDD1V8),
                .vssd1    (VSS),
                .vssd2    (VSS),
                .clock    (clock),
                .gpio     (gpio),
        .mprj_io  (mprj_io),
                .flash_csb(flash_csb),
                .flash_clk(flash_clk),
                .flash_io0(flash_io0),
                .flash_io1(flash_io1),
                .resetb   (RSTB)
        );
 
        spiflash #(
                .FILENAME("risc_boot.hex")
        ) spiflash (
                .csb(flash_csb),
                .clk(flash_clk),
                .io0(flash_io0),
                .io1(flash_io1),
                .io2(),                 // not used
                .io3()                  // not used
        );
 
//-----------------------------------------
// Connect Quad Flash to for usr Risc Core
//-----------------------------------------
 
   wire user_flash_clk = mprj_io[30];
   wire user_flash_csb = mprj_io[31];
   //tri  user_flash_io0 = mprj_io[33];
   //tri  user_flash_io1 = mprj_io[34];
   //tri  user_flash_io2 = mprj_io[35];
   //tri  user_flash_io3 = mprj_io[36];
 
   // Quard flash
        spiflash #(
                .FILENAME("user_risc_boot.hex")
        ) u_user_spiflash (
                .csb(user_flash_csb),
                .clk(user_flash_clk),
                .io0(mprj_io[32]),
                .io1(mprj_io[33]),
                .io2(mprj_io[34]),
                .io3(mprj_io[35])
        );
 
 
//------------------------------------------------
// Integrate the SDRAM 8 BIT Memory
// -----------------------------------------------
 
tri [7:0]    Dq                  ; // SDRAM Read/Write Data Bus
wire [0:0]    sdr_dqm            ; // SDRAM DATA Mask
wire [1:0]    sdr_ba             ; // SDRAM Bank Select
wire [12:0]   sdr_addr           ; // SDRAM ADRESS
wire          sdr_cs_n           ; // chip select
wire          sdr_cke            ; // clock gate
wire          sdr_ras_n          ; // ras
wire          sdr_cas_n          ; // cas
wire          sdr_we_n           ; // write enable        
wire          sdram_clk         ;
 
//assign  Dq[7:0]           =    mprj_io [7:0];
assign  sdr_addr[12:0]    =    mprj_io [20:8]     ;
assign  sdr_ba[1:0]       =    mprj_io [22:21]    ;
assign  sdr_dqm[0]        =    mprj_io [23]       ;
assign  sdr_we_n          =    mprj_io [24]       ;
assign  sdr_cas_n         =    mprj_io [25]       ;
assign  sdr_ras_n         =    mprj_io [26]       ;
assign  sdr_cs_n          =    mprj_io [27]       ;
assign  sdr_cke           =    mprj_io [28]       ;
assign  sdram_clk         =    mprj_io [29]       ;
 
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d   = sdram_clk;
 
        // SDRAM 8bit
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (mprj_io [7:0]      ) ,
          .Addr               (sdr_addr[11:0]     ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
 
 
 
/**
//-----------------------------------------------------------------------------
// RISC IMEM amd DMEM Monitoring TASK
//-----------------------------------------------------------------------------
logic [`SCR1_DMEM_AWIDTH-1:0]           core2imem_addr_o_r;           // DMEM address
logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o_r;           // DMEM address
logic                                   core2dmem_cmd_o_r;
 
`define RISC_CORE  test_tb.uut.mprj.u_core.u_riscv_top.i_core_top
 
always@(posedge `RISC_CORE.clk) begin
    if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
          core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
 
    if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
          core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
          core2dmem_cmd_o_r  <= `RISC_CORE.core2dmem_cmd_o;
    end
 
    if(`RISC_CORE.imem2core_resp_i !=0)
          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
    if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
    if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
end
*/
endmodule
`default_nettype wire

Browse

Tools

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [risc_boot/] [risc_boot_tb.v] - Blame information for rev 22

Line No.	Rev	Author	Line
1	22	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// User Risc Core Boot Validation ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 1. User Risc core is booted using compiled code of ////`
10			`//// user_risc_boot.hex ////`
11			`//// 2. User Risc core uses Serial Flash and SDRAM to boot ////`
12			`//// 3. After successful boot, Risc core will write signature////`
13			`//// in to user register from 0x3000_0018 to 0x3000_002C ////`
14			`//// 4. Through the External Wishbone Interface we read back ////`
15			`//// and validate the user register to declared pass fail ////`
16			`//// ////`
17			`//// To Do: ////`
18			`//// nothing ////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Dinesh Annayya, dinesha@opencores.org ////`
22			`//// ////`
23			`//// Revision : ////`
24			`//// 0.1 - 12th June 2021, Dinesh A ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27			`//// ////`
28			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
29			`//// ////`
30			`//// This source file may be used and distributed without ////`
31			`//// restriction provided that this copyright statement is not ////`
32			`//// removed from the file and that any derivative work contains ////`
33			`//// the original copyright notice and the associated disclaimer. ////`
34			`//// ////`
35			`//// This source file is free software; you can redistribute it ////`
36			`//// and/or modify it under the terms of the GNU Lesser General ////`
37			`//// Public License as published by the Free Software Foundation; ////`
38			`//// either version 2.1 of the License, or (at your option) any ////`
39			`//// later version. ////`
40			`//// ////`
41			`//// This source is distributed in the hope that it will be ////`
42			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
43			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
44			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
45			`//// details. ////`
46			`//// ////`
47			`//// You should have received a copy of the GNU Lesser General ////`
48			`//// Public License along with this source; if not, download it ////`
49			`//// from http://www.opencores.org/lgpl.shtml ////`
50			`//// ////`
51			`//////////////////////////////////////////////////////////////////////`
52
53			`default_nettype none
54
55			`timescale 1 ns / 1 ps
56
57			`include "uprj_netlists.v"
58			`include "caravel_netlists.v"
59			`include "spiflash.v"
60			`include "mt48lc8m8a2.v"
61
62			`module risc_boot_tb;`
63			`reg clock;`
64			`reg RSTB;`
65			`reg CSB;`
66			`reg power1, power2;`
67			`reg power3, power4;`
68
69			`wire gpio;`
70			`wire [37:0] mprj_io;`
71			`wire [7:0] mprj_io_0;`
72			`wire [15:0] checkbits;`
73
74			`assign checkbits = mprj_io[31:16];`
75
76			`assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;`
77
78			`// External clock is used by default. Make this artificially fast for the`
79			`// simulation. Normally this would be a slow clock and the digital PLL`
80			`// would be the fast clock.`
81
82			`always #12.5 clock <= (clock === 1'b0);`
83
84			`initial begin`
85			`clock = 0;`
86			`end`
87
88			`ifdef WFDUMP
89			`initial`
90			`begin`
91			`$dumpfile("simx.vcd");`
92			`$dumpvars(1,risc_boot_tb);`
93			`//$dumpvars(2,risc_boot_tb.uut);`
94			`$dumpvars(1,risc_boot_tb.uut.mprj.u_core);`
95			`//$dumpvars(0,risc_boot_tb.u_user_spiflash);`
96			`$display("Waveform Dump started");`
97			`end`
98			`endif
99
100			`initial begin`
101
102			`// Repeat cycles of 1000 clock edges as needed to complete testbench`
103			`repeat (600) begin`
104			`repeat (1000) @(posedge clock);`
105			`// $display("+1000 cycles");`
106			`end`
107			`$display("%c[1;31m",27);`
108			`ifdef GL
109			`$display ("Monitor: Timeout, Test user Risc Boot (GL) Failed");`
110			`else
111			`$display ("Monitor: Timeout, Test user Risc Boot (RTL) Failed");`
112			`endif
113			`$display("%c[0m",27);`
114			`$finish;`
115			`end`
116
117			`initial begin`
118			`wait(checkbits == 16'h AB60);`
119			`$display("Monitor: Test User Risc Boot Started");`
120			`wait(checkbits == 16'h AB61);`
121			`$display("#############################################");`
122			`ifdef GL
123			`$display("Monitor: Test User Risc Boot (GL) Passed");`
124			`else
125			`$display("Monitor: Test User Risc Boot (RTL) Passed");`
126			`endif
127			`$display("#############################################");`
128			`$finish;`
129			`end`
130
131			`initial begin`
132			`RSTB <= 1'b0;`
133			`CSB <= 1'b1; // Force CSB high`
134			`#2000;`
135			`RSTB <= 1'b1; // Release reset`
136			`#170000;`
137			`CSB = 1'b0; // CSB can be released`
138			`end`
139
140			`initial begin // Power-up sequence`
141			`power1 <= 1'b0;`
142			`power2 <= 1'b0;`
143			`power3 <= 1'b0;`
144			`power4 <= 1'b0;`
145			`#100;`
146			`power1 <= 1'b1;`
147			`#100;`
148			`power2 <= 1'b1;`
149			`#100;`
150			`power3 <= 1'b1;`
151			`#100;`
152			`power4 <= 1'b1;`
153			`end`
154
155			`//always @(mprj_io) begin`
156			`// #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);`
157			`//end`
158
159			`wire flash_csb;`
160			`wire flash_clk;`
161			`wire flash_io0;`
162			`wire flash_io1;`
163
164			`wire VDD3V3 = power1;`
165			`wire VDD1V8 = power2;`
166			`wire USER_VDD3V3 = power3;`
167			`wire USER_VDD1V8 = power4;`
168			`wire VSS = 1'b0;`
169
170			`caravel uut (`
171			`.vddio (VDD3V3),`
172			`.vssio (VSS),`
173			`.vdda (VDD3V3),`
174			`.vssa (VSS),`
175			`.vccd (VDD1V8),`
176			`.vssd (VSS),`
177			`.vdda1 (USER_VDD3V3),`
178			`.vdda2 (USER_VDD3V3),`
179			`.vssa1 (VSS),`
180			`.vssa2 (VSS),`
181			`.vccd1 (USER_VDD1V8),`
182			`.vccd2 (USER_VDD1V8),`
183			`.vssd1 (VSS),`
184			`.vssd2 (VSS),`
185			`.clock (clock),`
186			`.gpio (gpio),`
187			`.mprj_io (mprj_io),`
188			`.flash_csb(flash_csb),`
189			`.flash_clk(flash_clk),`
190			`.flash_io0(flash_io0),`
191			`.flash_io1(flash_io1),`
192			`.resetb (RSTB)`
193			`);`
194
195			`spiflash #(`
196			`.FILENAME("risc_boot.hex")`
197			`) spiflash (`
198			`.csb(flash_csb),`
199			`.clk(flash_clk),`
200			`.io0(flash_io0),`
201			`.io1(flash_io1),`
202			`.io2(), // not used`
203			`.io3() // not used`
204			`);`
205
206			`//-----------------------------------------`
207			`// Connect Quad Flash to for usr Risc Core`
208			`//-----------------------------------------`
209
210			`wire user_flash_clk = mprj_io[30];`
211			`wire user_flash_csb = mprj_io[31];`
212			`//tri user_flash_io0 = mprj_io[33];`
213			`//tri user_flash_io1 = mprj_io[34];`
214			`//tri user_flash_io2 = mprj_io[35];`
215			`//tri user_flash_io3 = mprj_io[36];`
216
217			`// Quard flash`
218			`spiflash #(`
219			`.FILENAME("user_risc_boot.hex")`
220			`) u_user_spiflash (`
221			`.csb(user_flash_csb),`
222			`.clk(user_flash_clk),`
223			`.io0(mprj_io[32]),`
224			`.io1(mprj_io[33]),`
225			`.io2(mprj_io[34]),`
226			`.io3(mprj_io[35])`
227			`);`
228
229
230			`//------------------------------------------------`
231			`// Integrate the SDRAM 8 BIT Memory`
232			`// -----------------------------------------------`
233
234			`tri [7:0] Dq ; // SDRAM Read/Write Data Bus`
235			`wire [0:0] sdr_dqm ; // SDRAM DATA Mask`
236			`wire [1:0] sdr_ba ; // SDRAM Bank Select`
237			`wire [12:0] sdr_addr ; // SDRAM ADRESS`
238			`wire sdr_cs_n ; // chip select`
239			`wire sdr_cke ; // clock gate`
240			`wire sdr_ras_n ; // ras`
241			`wire sdr_cas_n ; // cas`
242			`wire sdr_we_n ; // write enable`
243			`wire sdram_clk ;`
244
245			`//assign Dq[7:0] = mprj_io [7:0];`
246			`assign sdr_addr[12:0] = mprj_io [20:8] ;`
247			`assign sdr_ba[1:0] = mprj_io [22:21] ;`
248			`assign sdr_dqm[0] = mprj_io [23] ;`
249			`assign sdr_we_n = mprj_io [24] ;`
250			`assign sdr_cas_n = mprj_io [25] ;`
251			`assign sdr_ras_n = mprj_io [26] ;`
252			`assign sdr_cs_n = mprj_io [27] ;`
253			`assign sdr_cke = mprj_io [28] ;`
254			`assign sdram_clk = mprj_io [29] ;`
255
256			`// to fix the sdram interface timing issue`
257			`wire #(2.0) sdram_clk_d = sdram_clk;`
258
259			`// SDRAM 8bit`
260			`mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (`
261			`.Dq (mprj_io [7:0] ) ,`
262			`.Addr (sdr_addr[11:0] ),`
263			`.Ba (sdr_ba ),`
264			`.Clk (sdram_clk_d ),`
265			`.Cke (sdr_cke ),`
266			`.Cs_n (sdr_cs_n ),`
267			`.Ras_n (sdr_ras_n ),`
268			`.Cas_n (sdr_cas_n ),`
269			`.We_n (sdr_we_n ),`
270			`.Dqm (sdr_dqm )`
271			`);`
272
273
274
275			`/**`
276			`//-----------------------------------------------------------------------------`
277			`// RISC IMEM amd DMEM Monitoring TASK`
278			`//-----------------------------------------------------------------------------`
279			logic [`SCR1_DMEM_AWIDTH-1:0] core2imem_addr_o_r; // DMEM address
280			logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
281			`logic core2dmem_cmd_o_r;`
282
283			`define RISC_CORE test_tb.uut.mprj.u_core.u_riscv_top.i_core_top
284
285			always@(posedge `RISC_CORE.clk) begin
286			if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
287			core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
288
289			if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
290			core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
291			core2dmem_cmd_o_r <= `RISC_CORE.core2dmem_cmd_o;
292			`end`
293
294			if(`RISC_CORE.imem2core_resp_i !=0)
295			$display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
296			if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
297			$display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
298			if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
299			$display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
300			`end`
301			`*/`
302			`endmodule`
303			`default_nettype wire