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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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// Include caravel global defines for the number of the user project IO pads
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`define USE_POWER_PINS
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`include "spi_master/src/spim_top.sv"
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`include "spi_master/src/spim_regs.sv"
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`include "spi_master/src/spim_clkgen.sv"
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`include "spi_master/src/spim_ctrl.sv"
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`include "spi_master/src/spim_rx.sv"
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`include "spi_master/src/spim_tx.sv"
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`include "sdram_ctrl/src/top/sdrc_top.v"
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`include "sdram_ctrl/src/wb2sdrc/wb2sdrc.v"
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`include "lib/async_fifo.sv"
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`include "sdram_ctrl/src/core/sdrc_core.v"
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`include "sdram_ctrl/src/core/sdrc_bank_ctl.v"
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`include "sdram_ctrl/src/core/sdrc_bank_fsm.v"
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`include "sdram_ctrl/src/core/sdrc_bs_convert.v"
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`include "sdram_ctrl/src/core/sdrc_req_gen.v"
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`include "sdram_ctrl/src/core/sdrc_xfr_ctl.v"
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`include "lib/registers.v"
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`include "lib/clk_ctl.v"
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`include "digital_core/src/glbl_cfg.sv"
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`include "digital_core/src/digital_core.sv"
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`include "wb_interconnect/src/wb_arb.sv"
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`include "wb_interconnect/src/wb_interconnect.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
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`include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
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`include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
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`include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
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`include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
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`include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
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`include "syntacore/scr1/src/core/scr1_tapc.sv"
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`include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
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`include "syntacore/scr1/src/core/scr1_core_top.sv"
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`include "syntacore/scr1/src/core/scr1_dm.sv"
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`include "syntacore/scr1/src/core/scr1_dmi.sv"
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`include "syntacore/scr1/src/core/scr1_scu.sv"
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`include "syntacore/scr1/src/top/scr1_dmem_router.sv"
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`include "syntacore/scr1/src/top/scr1_dp_memory.sv"
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`include "syntacore/scr1/src/top/scr1_tcm.sv"
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`include "syntacore/scr1/src/top/scr1_timer.sv"
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`include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
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`include "syntacore/scr1/src/top/scr1_imem_wb.sv"
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`include "syntacore/scr1/src/top/scr1_top_wb.sv"
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`include "lib/sync_fifo.sv"
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