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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [user_risc_boot/] [user_risc_boot_tb.v] - Blame information for rev 22

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Standalone User validation Test bench                       ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
//     This is a standalone test bench to validate the            ////
//     Digital core.                                              ////
//     1. User Risc core is booted using  compiled code of        ////
//        user_risc_boot.c                                        ////
//     2. User Risc core uses Serial Flash and SDRAM to boot      ////
//     3. After successful boot, Risc core will  write signature  ////
//        in to  user register from 0x3000_0018 to 0x3000_002C    ////
//     4. Through the External Wishbone Interface we read back    ////
//         and validate the user register to declared pass fail   ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision :                                                  ////
////    0.1 - 16th Feb 2021, Dinesh A                             ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`default_nettype none
 
`timescale 1 ns / 1 ps
 
`include "uprj_netlists.v"
`include "spiflash.v"
`include "mt48lc8m8a2.v"
 
module user_risc_boot_tb;
        reg clock;
        reg RSTB;
        reg power1, power2;
        reg power3, power4;
 
        reg        wbd_ext_cyc_i;  // strobe/request
        reg        wbd_ext_stb_i;  // strobe/request
        reg [31:0] wbd_ext_adr_i;  // address
        reg        wbd_ext_we_i;  // write
        reg [31:0] wbd_ext_dat_i;  // data output
        reg [3:0]  wbd_ext_sel_i;  // byte enable
 
        wire [31:0] wbd_ext_dat_o;  // data input
        wire        wbd_ext_ack_o;  // acknowlegement
        wire        wbd_ext_err_o;  // error
 
        // User I/O
        wire [37:0] io_oeb;
        wire [37:0] io_out;
        wire [37:0] io_in;
 
        wire gpio;
        wire [37:0] mprj_io;
        wire [7:0] mprj_io_0;
        reg         test_fail;
        reg [31:0] read_data;
 
 
 
        // External clock is used by default.  Make this artificially fast for the
        // simulation.  Normally this would be a slow clock and the digital PLL
        // would be the fast clock.
 
        always #12.5 clock <= (clock === 1'b0);
 
        initial begin
                clock = 0;
                wbd_ext_cyc_i ='h0;  // strobe/request
                wbd_ext_stb_i ='h0;  // strobe/request
                wbd_ext_adr_i ='h0;  // address
                wbd_ext_we_i  ='h0;  // write
                wbd_ext_dat_i ='h0;  // data output
                wbd_ext_sel_i ='h0;  // byte enable
        end
 
        `ifdef WFDUMP
           initial begin
                $dumpfile("risc_boot.vcd");
                $dumpvars(0, user_risc_boot_tb);
           end
       `endif
 
        initial begin
 
                #200; // Wait for reset removal
                repeat (10) @(posedge clock);
                $display("Monitor: Standalone User Risc Boot Test Started");
 
                #1;
                //------------ SDRAM Config - 2
                wb_user_core_write('h3000_0014,'h100_019E);
 
                repeat (2) @(posedge clock);
                #1;
                //------------ SDRAM Config - 1
                wb_user_core_write('h3000_0010,'h2F17_2242);
 
                repeat (2) @(posedge clock);
                #1;
                // Remove all the reset
                wb_user_core_write('h3000_0000,'h7);
 
 
                // Repeat cycles of 1000 clock edges as needed to complete testbench
                repeat (30) begin
                        repeat (1000) @(posedge clock);
                        // $display("+1000 cycles");
                end
 
 
                $display("Monitor: Reading Back the expected value");
                // User RISC core expect to write these value in global
                // register, read back and decide on pass fail
                // 0x30000018  = 0x11223344; 
                // 0x3000001C  = 0x22334455; 
                // 0x30000020  = 0x33445566; 
                // 0x30000024  = 0x44556677; 
                // 0x30000028 = 0x55667788; 
                // 0x3000002C = 0x66778899; 
 
                test_fail = 0;
                wb_user_core_read(32'h30000018,read_data);
                if(read_data != 32'h11223344) test_fail = 1;
 
                wb_user_core_read(32'h3000001C,read_data);
                if(read_data != 32'h22334455) test_fail = 1;
 
                wb_user_core_read(32'h30000020,read_data);
                if(read_data != 32'h33445566) test_fail = 1;
 
                wb_user_core_read(32'h30000024,read_data);
                if(read_data!= 32'h44556677) test_fail = 1;
 
                wb_user_core_read(32'h30000028,read_data);
                if(read_data!= 32'h55667788) test_fail = 1;
 
                wb_user_core_read(32'h3000002C,read_data) ;
                if(read_data != 32'h66778899) test_fail = 1;
 
 
                $display("###################################################");
                if(test_fail == 0) begin
                   `ifdef GL
                       $display("Monitor: Standalone User Risc Boot (GL) Passed");
                   `else
                       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
                   `endif
                end else begin
                    `ifdef GL
                        $display("Monitor: Standalone User Risc Boot (GL) Failed");
                    `else
                        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
                    `endif
                 end
                $display("###################################################");
            $finish;
        end
 
        initial begin
                RSTB <= 1'b0;
                #100;
                RSTB <= 1'b1;           // Release reset
        end
 
 
 digital_core u_core(
`ifdef USE_POWER_PINS
    .vdda1(),   // User area 1 3.3V supply
    .vdda2(),   // User area 2 3.3V supply
    .vssa1(),   // User area 1 analog ground
    .vssa2(),   // User area 2 analog ground
    .vccd1(),   // User area 1 1.8V supply
    .vccd2(),   // User area 2 1.8v supply
    .vssd1(),   // User area 1 digital ground
    .vssd2(),   // User area 2 digital ground
`endif
    .clk             (clock),  // System clock
    .rtc_clk         (1'b1),  // Real-time clock
    .rst_n           (RSTB),  // Regular Reset signal
 
    .wbd_ext_cyc_i   (wbd_ext_cyc_i),  // strobe/request
    .wbd_ext_stb_i   (wbd_ext_stb_i),  // strobe/request
    .wbd_ext_adr_i   (wbd_ext_adr_i),  // address
    .wbd_ext_we_i    (wbd_ext_we_i),  // write
    .wbd_ext_dat_i   (wbd_ext_dat_i),  // data output
    .wbd_ext_sel_i   (wbd_ext_sel_i),  // byte enable
 
    .wbd_ext_dat_o   (wbd_ext_dat_o),  // data input
    .wbd_ext_ack_o   (wbd_ext_ack_o),  // acknowlegement
    .wbd_ext_err_o   (wbd_ext_err_o),  // error
 
 
    // Logic Analyzer Signals
    .la_data_in      ('0) ,
    .la_data_out     (),
    .la_oenb         ('0),
 
 
    // IOs
    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,
 
    .irq            ()
 
);
 
//------------------------------------------------------
//  Integrate the Serial flash with qurd support to
//  user core using the gpio pads
//  ----------------------------------------------------
 
   wire flash_clk = io_out[30];
   wire flash_csb = io_out[31];
   tri  flash_io0 = (io_oeb[32]== 1'b0) ? io_out[32] : 1'bz;
   tri  flash_io1 = (io_oeb[33]== 1'b0) ? io_out[33] : 1'bz;
   tri  flash_io2 = (io_oeb[34]== 1'b0) ? io_out[34] : 1'bz;
   tri  flash_io3 = (io_oeb[35]== 1'b0) ? io_out[35] : 1'bz;
 
   assign io_in[32] = flash_io0;
   assign io_in[33] = flash_io1;
   assign io_in[34] = flash_io2;
   assign io_in[35] = flash_io3;
 
 
   // Quard flash
        spiflash #(
                .FILENAME("user_risc_boot.hex")
        ) u_user_spiflash (
                .csb(flash_csb),
                .clk(flash_clk),
                .io0(flash_io0),
                .io1(flash_io1),
                .io2(flash_io2),
                .io3(flash_io3)
        );
 
 
//------------------------------------------------
// Integrate the SDRAM 8 BIT Memory
// -----------------------------------------------
 
wire [7:0]    Dq                 ; // SDRAM Read/Write Data Bus
wire [0:0]    sdr_dqm            ; // SDRAM DATA Mask
wire [1:0]    sdr_ba             ; // SDRAM Bank Select
wire [12:0]   sdr_addr           ; // SDRAM ADRESS
wire          sdr_cs_n           ; // chip select
wire          sdr_cke            ; // clock gate
wire          sdr_ras_n          ; // ras
wire          sdr_cas_n          ; // cas
wire          sdr_we_n           ; // write enable        
wire          sdram_clk         ;
 
assign  Dq[7:0]           =  (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;
assign  sdr_addr[12:0]    =    io_out [20:8]     ;
assign  sdr_ba[1:0]       =    io_out [22:21]    ;
assign  sdr_dqm[0]        =    io_out [23]       ;
assign  sdr_we_n          =    io_out [24]       ;
assign  sdr_cas_n         =    io_out [25]       ;
assign  sdr_ras_n         =    io_out [26]       ;
assign  sdr_cs_n          =    io_out [27]       ;
assign  sdr_cke           =    io_out [28]       ;
assign  sdram_clk         =    io_out [29]       ;
assign  io_in[29]         =    sdram_clk;
assign  #(1) io_in[7:0]   =    Dq;
 
// to fix the sdram interface timing issue
wire #(1) sdram_clk_d   = sdram_clk;
 
        // SDRAM 8bit
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
          .Dq                 (Dq                 ) ,
          .Addr               (sdr_addr[11:0]     ),
          .Ba                 (sdr_ba             ),
          .Clk                (sdram_clk_d        ),
          .Cke                (sdr_cke            ),
          .Cs_n               (sdr_cs_n           ),
          .Ras_n              (sdr_ras_n          ),
          .Cas_n              (sdr_cas_n          ),
          .We_n               (sdr_we_n           ),
          .Dqm                (sdr_dqm            )
     );
 
 
task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  wbd_ext_adr_i =address;  // address
  wbd_ext_we_i  ='h1;  // write
  wbd_ext_dat_i =data;  // data output
  wbd_ext_sel_i ='hF;  // byte enable
  wbd_ext_cyc_i ='h1;  // strobe/request
  wbd_ext_stb_i ='h1;  // strobe/request
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  wbd_ext_cyc_i ='h0;  // strobe/request
  wbd_ext_stb_i ='h0;  // strobe/request
  wbd_ext_adr_i ='h0;  // address
  wbd_ext_we_i  ='h0;  // write
  wbd_ext_dat_i ='h0;  // data output
  wbd_ext_sel_i ='h0;  // byte enable
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask
 
task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  wbd_ext_adr_i =address;  // address
  wbd_ext_we_i  ='h0;  // write
  wbd_ext_dat_i ='0;  // data output
  wbd_ext_sel_i ='hF;  // byte enable
  wbd_ext_cyc_i ='h1;  // strobe/request
  wbd_ext_stb_i ='h1;  // strobe/request
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;
  repeat (1) @(posedge clock);
  wbd_ext_cyc_i ='h0;  // strobe/request
  wbd_ext_stb_i ='h0;  // strobe/request
  wbd_ext_adr_i ='h0;  // address
  wbd_ext_we_i  ='h0;  // write
  wbd_ext_dat_i ='h0;  // data output
  wbd_ext_sel_i ='h0;  // byte enable
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask
 
 
 
 
////-----------------------------------------------------------------------------
//// RISC IMEM amd DMEM Monitoring TASK
////-----------------------------------------------------------------------------
//logic [`SCR1_DMEM_AWIDTH-1:0]           core2imem_addr_o_r;           // DMEM address
//logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o_r;           // DMEM address
//logic                                   core2dmem_cmd_o_r;
//
//`define RISC_CORE  user_risc_boot_tb.u_core.u_riscv_top.i_core_top
//
//always@(posedge `RISC_CORE.clk) begin
//    if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
//          core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
//
//    if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
//          core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
//          core2dmem_cmd_o_r  <= `RISC_CORE.core2dmem_cmd_o;
//    end
//
//    if(`RISC_CORE.imem2core_resp_i !=0)
//          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
//    if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
//          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
//    if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
//          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
//end
endmodule
`default_nettype wire

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [user_risc_boot/] [user_risc_boot_tb.v] - Blame information for rev 22

Line No.	Rev	Author	Line
1	22	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Standalone User validation Test bench ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`// This is a standalone test bench to validate the ////`
10			`// Digital core. ////`
11			`// 1. User Risc core is booted using compiled code of ////`
12			`// user_risc_boot.c ////`
13			`// 2. User Risc core uses Serial Flash and SDRAM to boot ////`
14			`// 3. After successful boot, Risc core will write signature ////`
15			`// in to user register from 0x3000_0018 to 0x3000_002C ////`
16			`// 4. Through the External Wishbone Interface we read back ////`
17			`// and validate the user register to declared pass fail ////`
18			`//// ////`
19			`//// To Do: ////`
20			`//// nothing ////`
21			`//// ////`
22			`//// Author(s): ////`
23			`//// - Dinesh Annayya, dinesha@opencores.org ////`
24			`//// ////`
25			`//// Revision : ////`
26			`//// 0.1 - 16th Feb 2021, Dinesh A ////`
27			`//// ////`
28			`//////////////////////////////////////////////////////////////////////`
29			`//// ////`
30			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
31			`//// ////`
32			`//// This source file may be used and distributed without ////`
33			`//// restriction provided that this copyright statement is not ////`
34			`//// removed from the file and that any derivative work contains ////`
35			`//// the original copyright notice and the associated disclaimer. ////`
36			`//// ////`
37			`//// This source file is free software; you can redistribute it ////`
38			`//// and/or modify it under the terms of the GNU Lesser General ////`
39			`//// Public License as published by the Free Software Foundation; ////`
40			`//// either version 2.1 of the License, or (at your option) any ////`
41			`//// later version. ////`
42			`//// ////`
43			`//// This source is distributed in the hope that it will be ////`
44			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
45			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
46			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
47			`//// details. ////`
48			`//// ////`
49			`//// You should have received a copy of the GNU Lesser General ////`
50			`//// Public License along with this source; if not, download it ////`
51			`//// from http://www.opencores.org/lgpl.shtml ////`
52			`//// ////`
53			`//////////////////////////////////////////////////////////////////////`
54
55			`default_nettype none
56
57			`timescale 1 ns / 1 ps
58
59			`include "uprj_netlists.v"
60			`include "spiflash.v"
61			`include "mt48lc8m8a2.v"
62
63			`module user_risc_boot_tb;`
64			`reg clock;`
65			`reg RSTB;`
66			`reg power1, power2;`
67			`reg power3, power4;`
68
69			`reg wbd_ext_cyc_i; // strobe/request`
70			`reg wbd_ext_stb_i; // strobe/request`
71			`reg [31:0] wbd_ext_adr_i; // address`
72			`reg wbd_ext_we_i; // write`
73			`reg [31:0] wbd_ext_dat_i; // data output`
74			`reg [3:0] wbd_ext_sel_i; // byte enable`
75
76			`wire [31:0] wbd_ext_dat_o; // data input`
77			`wire wbd_ext_ack_o; // acknowlegement`
78			`wire wbd_ext_err_o; // error`
79
80			`// User I/O`
81			`wire [37:0] io_oeb;`
82			`wire [37:0] io_out;`
83			`wire [37:0] io_in;`
84
85			`wire gpio;`
86			`wire [37:0] mprj_io;`
87			`wire [7:0] mprj_io_0;`
88			`reg test_fail;`
89			`reg [31:0] read_data;`
90
91
92
93			`// External clock is used by default. Make this artificially fast for the`
94			`// simulation. Normally this would be a slow clock and the digital PLL`
95			`// would be the fast clock.`
96
97			`always #12.5 clock <= (clock === 1'b0);`
98
99			`initial begin`
100			`clock = 0;`
101			`wbd_ext_cyc_i ='h0; // strobe/request`
102			`wbd_ext_stb_i ='h0; // strobe/request`
103			`wbd_ext_adr_i ='h0; // address`
104			`wbd_ext_we_i ='h0; // write`
105			`wbd_ext_dat_i ='h0; // data output`
106			`wbd_ext_sel_i ='h0; // byte enable`
107			`end`
108
109			`ifdef WFDUMP
110			`initial begin`
111			`$dumpfile("risc_boot.vcd");`
112			`$dumpvars(0, user_risc_boot_tb);`
113			`end`
114			`endif
115
116			`initial begin`
117
118			`#200; // Wait for reset removal`
119			`repeat (10) @(posedge clock);`
120			`$display("Monitor: Standalone User Risc Boot Test Started");`
121
122			`#1;`
123			`//------------ SDRAM Config - 2`
124			`wb_user_core_write('h3000_0014,'h100_019E);`
125
126			`repeat (2) @(posedge clock);`
127			`#1;`
128			`//------------ SDRAM Config - 1`
129			`wb_user_core_write('h3000_0010,'h2F17_2242);`
130
131			`repeat (2) @(posedge clock);`
132			`#1;`
133			`// Remove all the reset`
134			`wb_user_core_write('h3000_0000,'h7);`
135
136
137			`// Repeat cycles of 1000 clock edges as needed to complete testbench`
138			`repeat (30) begin`
139			`repeat (1000) @(posedge clock);`
140			`// $display("+1000 cycles");`
141			`end`
142
143
144			`$display("Monitor: Reading Back the expected value");`
145			`// User RISC core expect to write these value in global`
146			`// register, read back and decide on pass fail`
147			`// 0x30000018 = 0x11223344;`
148			`// 0x3000001C = 0x22334455;`
149			`// 0x30000020 = 0x33445566;`
150			`// 0x30000024 = 0x44556677;`
151			`// 0x30000028 = 0x55667788;`
152			`// 0x3000002C = 0x66778899;`
153
154			`test_fail = 0;`
155			`wb_user_core_read(32'h30000018,read_data);`
156			`if(read_data != 32'h11223344) test_fail = 1;`
157
158			`wb_user_core_read(32'h3000001C,read_data);`
159			`if(read_data != 32'h22334455) test_fail = 1;`
160
161			`wb_user_core_read(32'h30000020,read_data);`
162			`if(read_data != 32'h33445566) test_fail = 1;`
163
164			`wb_user_core_read(32'h30000024,read_data);`
165			`if(read_data!= 32'h44556677) test_fail = 1;`
166
167			`wb_user_core_read(32'h30000028,read_data);`
168			`if(read_data!= 32'h55667788) test_fail = 1;`
169
170			`wb_user_core_read(32'h3000002C,read_data) ;`
171			`if(read_data != 32'h66778899) test_fail = 1;`
172
173
174			`$display("###################################################");`
175			`if(test_fail == 0) begin`
176			`ifdef GL
177			`$display("Monitor: Standalone User Risc Boot (GL) Passed");`
178			`else
179			`$display("Monitor: Standalone User Risc Boot (RTL) Passed");`
180			`endif
181			`end else begin`
182			`ifdef GL
183			`$display("Monitor: Standalone User Risc Boot (GL) Failed");`
184			`else
185			`$display("Monitor: Standalone User Risc Boot (RTL) Failed");`
186			`endif
187			`end`
188			`$display("###################################################");`
189			`$finish;`
190			`end`
191
192			`initial begin`
193			`RSTB <= 1'b0;`
194			`#100;`
195			`RSTB <= 1'b1; // Release reset`
196			`end`
197
198
199			`digital_core u_core(`
200			`ifdef USE_POWER_PINS
201			`.vdda1(), // User area 1 3.3V supply`
202			`.vdda2(), // User area 2 3.3V supply`
203			`.vssa1(), // User area 1 analog ground`
204			`.vssa2(), // User area 2 analog ground`
205			`.vccd1(), // User area 1 1.8V supply`
206			`.vccd2(), // User area 2 1.8v supply`
207			`.vssd1(), // User area 1 digital ground`
208			`.vssd2(), // User area 2 digital ground`
209			`endif
210			`.clk (clock), // System clock`
211			`.rtc_clk (1'b1), // Real-time clock`
212			`.rst_n (RSTB), // Regular Reset signal`
213
214			`.wbd_ext_cyc_i (wbd_ext_cyc_i), // strobe/request`
215			`.wbd_ext_stb_i (wbd_ext_stb_i), // strobe/request`
216			`.wbd_ext_adr_i (wbd_ext_adr_i), // address`
217			`.wbd_ext_we_i (wbd_ext_we_i), // write`
218			`.wbd_ext_dat_i (wbd_ext_dat_i), // data output`
219			`.wbd_ext_sel_i (wbd_ext_sel_i), // byte enable`
220
221			`.wbd_ext_dat_o (wbd_ext_dat_o), // data input`
222			`.wbd_ext_ack_o (wbd_ext_ack_o), // acknowlegement`
223			`.wbd_ext_err_o (wbd_ext_err_o), // error`
224
225
226			`// Logic Analyzer Signals`
227			`.la_data_in ('0) ,`
228			`.la_data_out (),`
229			`.la_oenb ('0),`
230
231
232			`// IOs`
233			`.io_in (io_in) ,`
234			`.io_out (io_out) ,`
235			`.io_oeb (io_oeb) ,`
236
237			`.irq ()`
238
239			`);`
240
241			`//------------------------------------------------------`
242			`// Integrate the Serial flash with qurd support to`
243			`// user core using the gpio pads`
244			`// ----------------------------------------------------`
245
246			`wire flash_clk = io_out[30];`
247			`wire flash_csb = io_out[31];`
248			`tri flash_io0 = (io_oeb[32]== 1'b0) ? io_out[32] : 1'bz;`
249			`tri flash_io1 = (io_oeb[33]== 1'b0) ? io_out[33] : 1'bz;`
250			`tri flash_io2 = (io_oeb[34]== 1'b0) ? io_out[34] : 1'bz;`
251			`tri flash_io3 = (io_oeb[35]== 1'b0) ? io_out[35] : 1'bz;`
252
253			`assign io_in[32] = flash_io0;`
254			`assign io_in[33] = flash_io1;`
255			`assign io_in[34] = flash_io2;`
256			`assign io_in[35] = flash_io3;`
257
258
259			`// Quard flash`
260			`spiflash #(`
261			`.FILENAME("user_risc_boot.hex")`
262			`) u_user_spiflash (`
263			`.csb(flash_csb),`
264			`.clk(flash_clk),`
265			`.io0(flash_io0),`
266			`.io1(flash_io1),`
267			`.io2(flash_io2),`
268			`.io3(flash_io3)`
269			`);`
270
271
272			`//------------------------------------------------`
273			`// Integrate the SDRAM 8 BIT Memory`
274			`// -----------------------------------------------`
275
276			`wire [7:0] Dq ; // SDRAM Read/Write Data Bus`
277			`wire [0:0] sdr_dqm ; // SDRAM DATA Mask`
278			`wire [1:0] sdr_ba ; // SDRAM Bank Select`
279			`wire [12:0] sdr_addr ; // SDRAM ADRESS`
280			`wire sdr_cs_n ; // chip select`
281			`wire sdr_cke ; // clock gate`
282			`wire sdr_ras_n ; // ras`
283			`wire sdr_cas_n ; // cas`
284			`wire sdr_we_n ; // write enable`
285			`wire sdram_clk ;`
286
287			`assign Dq[7:0] = (io_oeb[7:0] == 8'h0) ? io_out [7:0] : 8'hZZ;`
288			`assign sdr_addr[12:0] = io_out [20:8] ;`
289			`assign sdr_ba[1:0] = io_out [22:21] ;`
290			`assign sdr_dqm[0] = io_out [23] ;`
291			`assign sdr_we_n = io_out [24] ;`
292			`assign sdr_cas_n = io_out [25] ;`
293			`assign sdr_ras_n = io_out [26] ;`
294			`assign sdr_cs_n = io_out [27] ;`
295			`assign sdr_cke = io_out [28] ;`
296			`assign sdram_clk = io_out [29] ;`
297			`assign io_in[29] = sdram_clk;`
298			`assign #(1) io_in[7:0] = Dq;`
299
300			`// to fix the sdram interface timing issue`
301			`wire #(1) sdram_clk_d = sdram_clk;`
302
303			`// SDRAM 8bit`
304			`mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (`
305			`.Dq (Dq ) ,`
306			`.Addr (sdr_addr[11:0] ),`
307			`.Ba (sdr_ba ),`
308			`.Clk (sdram_clk_d ),`
309			`.Cke (sdr_cke ),`
310			`.Cs_n (sdr_cs_n ),`
311			`.Ras_n (sdr_ras_n ),`
312			`.Cas_n (sdr_cas_n ),`
313			`.We_n (sdr_we_n ),`
314			`.Dqm (sdr_dqm )`
315			`);`
316
317
318			`task wb_user_core_write;`
319			`input [31:0] address;`
320			`input [31:0] data;`
321			`begin`
322			`repeat (1) @(posedge clock);`
323			`wbd_ext_adr_i =address; // address`
324			`wbd_ext_we_i ='h1; // write`
325			`wbd_ext_dat_i =data; // data output`
326			`wbd_ext_sel_i ='hF; // byte enable`
327			`wbd_ext_cyc_i ='h1; // strobe/request`
328			`wbd_ext_stb_i ='h1; // strobe/request`
329			`wait(wbd_ext_ack_o == 1);`
330			`repeat (1) @(posedge clock);`
331			`wbd_ext_cyc_i ='h0; // strobe/request`
332			`wbd_ext_stb_i ='h0; // strobe/request`
333			`wbd_ext_adr_i ='h0; // address`
334			`wbd_ext_we_i ='h0; // write`
335			`wbd_ext_dat_i ='h0; // data output`
336			`wbd_ext_sel_i ='h0; // byte enable`
337			`$display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);`
338			`repeat (2) @(posedge clock);`
339			`end`
340			`endtask`
341
342			`task wb_user_core_read;`
343			`input [31:0] address;`
344			`output [31:0] data;`
345			`reg [31:0] data;`
346			`begin`
347			`repeat (1) @(posedge clock);`
348			`wbd_ext_adr_i =address; // address`
349			`wbd_ext_we_i ='h0; // write`
350			`wbd_ext_dat_i ='0; // data output`
351			`wbd_ext_sel_i ='hF; // byte enable`
352			`wbd_ext_cyc_i ='h1; // strobe/request`
353			`wbd_ext_stb_i ='h1; // strobe/request`
354			`wait(wbd_ext_ack_o == 1);`
355			`data = wbd_ext_dat_o;`
356			`repeat (1) @(posedge clock);`
357			`wbd_ext_cyc_i ='h0; // strobe/request`
358			`wbd_ext_stb_i ='h0; // strobe/request`
359			`wbd_ext_adr_i ='h0; // address`
360			`wbd_ext_we_i ='h0; // write`
361			`wbd_ext_dat_i ='h0; // data output`
362			`wbd_ext_sel_i ='h0; // byte enable`
363			`$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);`
364			`repeat (2) @(posedge clock);`
365			`end`
366			`endtask`
367
368
369
370
371			`////-----------------------------------------------------------------------------`
372			`//// RISC IMEM amd DMEM Monitoring TASK`
373			`////-----------------------------------------------------------------------------`
374			//logic [`SCR1_DMEM_AWIDTH-1:0] core2imem_addr_o_r; // DMEM address
375			//logic [`SCR1_DMEM_AWIDTH-1:0] core2dmem_addr_o_r; // DMEM address
376			`//logic core2dmem_cmd_o_r;`
377			`//`
378			//`define RISC_CORE user_risc_boot_tb.u_core.u_riscv_top.i_core_top
379			`//`
380			//always@(posedge `RISC_CORE.clk) begin
381			// if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
382			// core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
383			`//`
384			// if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
385			// core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
386			// core2dmem_cmd_o_r <= `RISC_CORE.core2dmem_cmd_o;
387			`// end`
388			`//`
389			// if(`RISC_CORE.imem2core_resp_i !=0)
390			// $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
391			// if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
392			// $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
393			// if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
394			// $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
395			`//end`
396			`endmodule`
397			`default_nettype wire