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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [digital_core/] [filelist_rtl.f] - Blame information for rev 20

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Line No. Rev Author Line
1 20 dinesha
 
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+incdir+../sdram_ctrl/src/defs
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+incdir+../syntacore/scr1/src/includes
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../spi_master/src/spim_top.sv
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../spi_master/src/spim_regs.sv
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../spi_master/src/spim_clkgen.sv
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../spi_master/src/spim_ctrl.sv
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../spi_master/src/spim_rx.sv
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../spi_master/src/spim_tx.sv
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../sdram_ctrl/src/top/sdrc_top.v
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../sdram_ctrl/src/wb2sdrc/wb2sdrc.v
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../lib/async_fifo.sv
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../sdram_ctrl/src/core/sdrc_core.v
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../sdram_ctrl/src/core/sdrc_bank_ctl.v
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../sdram_ctrl/src/core/sdrc_bank_fsm.v
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../sdram_ctrl/src/core/sdrc_bs_convert.v
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../sdram_ctrl/src/core/sdrc_req_gen.v
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../sdram_ctrl/src/core/sdrc_xfr_ctl.v
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../lib/wb_crossbar.v
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./src/digital_core.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv
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../syntacore/scr1/src/core/pipeline/scr1_ipic.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
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../syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
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../syntacore/scr1/src/core/primitives/scr1_reset_cells.sv
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../syntacore/scr1/src/core/primitives/scr1_cg.sv
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../syntacore/scr1/src/core/scr1_clk_ctrl.sv
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../syntacore/scr1/src/core/scr1_tapc_shift_reg.sv
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../syntacore/scr1/src/core/scr1_tapc.sv
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../syntacore/scr1/src/core/scr1_tapc_synchronizer.sv
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../syntacore/scr1/src/core/scr1_core_top.sv
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../syntacore/scr1/src/core/scr1_dm.sv
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../syntacore/scr1/src/core/scr1_dmi.sv
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../syntacore/scr1/src/core/scr1_scu.sv
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../syntacore/scr1/src/top/scr1_dmem_router.sv
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../syntacore/scr1/src/top/scr1_dp_memory.sv
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../syntacore/scr1/src/top/scr1_tcm.sv
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../syntacore/scr1/src/top/scr1_timer.sv
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../syntacore/scr1/src/top/scr1_dmem_wb.sv
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../syntacore/scr1/src/top/scr1_imem_wb.sv
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../syntacore/scr1/src/top/scr1_top_wb.sv
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../lib/sync_fifo.sv
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