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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [lib/] [clk_ctl.v] - Blame information for rev 22

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Tubo 8051 cores common library Module                       ////
////                                                              ////
////  This file is part of the Turbo 8051 cores project           ////
////  http://www.opencores.org/cores/turbo8051/                   ////
////                                                              ////
////  Description                                                 ////
////  Turbo 8051 definitions.                                     ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : Mar 2, 2011                                      //// 
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// #################################################################
// Module: clk_ctl
//
// Description:  Generic clock control logic , clk-out = mclk/(2+clk_div_ratio)
//
//  
// #################################################################
 
 
module clk_ctl (
   // Outputs
       clk_o,
   // Inputs
       mclk,
       reset_n,
       clk_div_ratio
   );
 
//---------------------------------
// CLOCK Default Divider value.
// This value will be change from outside
//---------------------------------
parameter  WD = 'h1;
 
//---------------------------------------------
// All the input to this block are declared here
// --------------------------------------------
   input        mclk          ;// 
   input        reset_n       ;// primary reset signal
   input [WD:0] clk_div_ratio ;// primary clock divide ratio
                               // output clock = selected clock / (div_ratio+1)
 
//---------------------------------------------
// All the output to this block are declared here
// --------------------------------------------
   output       clk_o             ; // clock out
 
 
 
//------------------------------------
// Clock Divide func is done here
//------------------------------------
reg  [WD-1:0]    high_count       ; // high level counter
reg  [WD-1:0]    low_count        ; // low level counter
reg              mclk_div         ; // divided clock
 
 
assign clk_o  = mclk_div;
 
always @ (posedge mclk or negedge reset_n)
begin // {
   if(reset_n == 1'b0)
   begin
      high_count  <= 'h0;
      low_count   <= 'h0;
      mclk_div    <= 'b0;
   end
   else
   begin
      if(high_count != 0)
      begin // {
         high_count    <= high_count - 1;
         mclk_div      <= 1'b1;
      end   // }
      else if(low_count != 0)
      begin // {
         low_count     <= low_count - 1;
         mclk_div      <= 1'b0;
      end   // }
      else
      begin // {
         high_count    <= clk_div_ratio[WD:1] + clk_div_ratio[0];
         low_count     <= clk_div_ratio[WD:1] + 1;
         mclk_div      <= ~mclk_div;
      end   // }
   end   // }
end   // }
 
 
endmodule
 

Line No.	Rev	Author	Line
1	22	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Tubo 8051 cores common library Module ////`
4			`//// ////`
5			`//// This file is part of the Turbo 8051 cores project ////`
6			`//// http://www.opencores.org/cores/turbo8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Turbo 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : Mar 2, 2011 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45
46			`// #################################################################`
47			`// Module: clk_ctl`
48			`//`
49			`// Description: Generic clock control logic , clk-out = mclk/(2+clk_div_ratio)`
50			`//`
51			`//`
52			`// #################################################################`
53
54
55			`module clk_ctl (`
56			`// Outputs`
57			`clk_o,`
58			`// Inputs`
59			`mclk,`
60			`reset_n,`
61			`clk_div_ratio`
62			`);`
63
64			`//---------------------------------`
65			`// CLOCK Default Divider value.`
66			`// This value will be change from outside`
67			`//---------------------------------`
68			`parameter WD = 'h1;`
69
70			`//---------------------------------------------`
71			`// All the input to this block are declared here`
72			`// --------------------------------------------`
73			`input mclk ;//`
74			`input reset_n ;// primary reset signal`
75			`input [WD:0] clk_div_ratio ;// primary clock divide ratio`
76			`// output clock = selected clock / (div_ratio+1)`
77
78			`//---------------------------------------------`
79			`// All the output to this block are declared here`
80			`// --------------------------------------------`
81			`output clk_o ; // clock out`
82
83
84
85			`//------------------------------------`
86			`// Clock Divide func is done here`
87			`//------------------------------------`
88			`reg [WD-1:0] high_count ; // high level counter`
89			`reg [WD-1:0] low_count ; // low level counter`
90			`reg mclk_div ; // divided clock`
91
92
93			`assign clk_o = mclk_div;`
94
95			`always @ (posedge mclk or negedge reset_n)`
96			`begin // {`
97			`if(reset_n == 1'b0)`
98			`begin`
99			`high_count <= 'h0;`
100			`low_count <= 'h0;`
101			`mclk_div <= 'b0;`
102			`end`
103			`else`
104			`begin`
105			`if(high_count != 0)`
106			`begin // {`
107			`high_count <= high_count - 1;`
108			`mclk_div <= 1'b1;`
109			`end // }`
110			`else if(low_count != 0)`
111			`begin // {`
112			`low_count <= low_count - 1;`
113			`mclk_div <= 1'b0;`
114			`end // }`
115			`else`
116			`begin // {`
117			`high_count <= clk_div_ratio[WD:1] + clk_div_ratio[0];`
118			`low_count <= clk_div_ratio[WD:1] + 1;`
119			`mclk_div <= ~mclk_div;`
120			`end // }`
121			`end // }`
122			`end // }`
123
124
125			`endmodule`
126

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [lib/] [clk_ctl.v] - Blame information for rev 22