URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [lib/] [sync_fifo.sv] - Blame information for rev 18

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  YiFive cores common library Module                          ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////     Sync Fifo with full and empty                            ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : June 7, 2021                                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module sync_fifo #(
      parameter  DATA_WIDTH  = 32, // Data Width
      parameter  ADDR_WIDTH   = 1,  // Address Width
      parameter  FIFO_DEPTH   = 2 // FIFO DEPTH
 
)(
       output [DATA_WIDTH-1:0] dout,
       input                    rstn,
       input                    clk,
       input                    wr_en, // Write
       input                    rd_en, // Read
       input [DATA_WIDTH-1:0]  din,
       output                  full,
       output                  empty
);
 
 
reg [DATA_WIDTH-1:0]  ram [FIFO_DEPTH-1:0];
reg [ADDR_WIDTH-1:0]  wptr; // write ptr
reg [ADDR_WIDTH-1:0]  rptr; // write ptr
reg [ADDR_WIDTH:0]    status_cnt; // status counter
reg                   empty;
reg                   full;
 
 
 //-----------Code Start---------------------------
 always @ (negedge rstn or posedge clk)
 begin : WRITE_POINTER
   if (rstn==1'b0) begin
     wptr <= 0;
   end else if (wr_en ) begin
     wptr <= wptr + 1;
   end
 end
 
always @ (negedge rstn or posedge clk)
begin : READ_POINTER
  if (rstn==1'b0) begin
    rptr <= 0;
  end else if (rd_en) begin
    rptr <= rptr + 1;
  end
end
 
always @ (negedge rstn or posedge clk)
begin : STATUS_COUNTER
  if (rstn==1'b0) begin
       status_cnt <= 0;
  // Read but no write.
  end else if (rd_en &&   (!wr_en) && (status_cnt  != 0)) begin
    status_cnt <= status_cnt - 1;
  // Write but no read.
  end else if (wr_en &&  (!rd_en) && (status_cnt  != FIFO_DEPTH)) begin
    status_cnt <= status_cnt + 1;
  end
end
 
// underflow is not handled
always @ (negedge rstn or posedge clk)
begin : EMPTY_FLAG
  if (rstn==1'b0) begin
       empty <= 1;
  // Read but no write.
  end else if (rd_en &&   (!wr_en) && (status_cnt  == 1)) begin
    empty <= 1;
  // Write
  end else if (wr_en) begin
    empty <= 0;
  end else if (status_cnt  == 0) begin
     empty <= 1;
  end
end
 
// overflow is not handled
always @ (negedge rstn or posedge clk)
begin : FULL_FLAG
  if (rstn==1'b0) begin
       full <= 0;
  // Write but no read.
  end else if (wr_en &&  (!rd_en) && (status_cnt  == (FIFO_DEPTH-1))) begin
    full <= 1;
  // Read
  end else if (rd_en &&  (!wr_en) ) begin
    full <= 0;
  end else if (status_cnt  == FIFO_DEPTH) begin
     full <= 1;
  end
end
assign dout = ram[rptr];
 
always @ (posedge clk)
begin
  if (wr_en) ram[wptr] <= din;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	11	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// YiFive cores common library Module ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Sync Fifo with full and empty ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : June 7, 2021 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45
46			`module sync_fifo #(`
47			`parameter DATA_WIDTH = 32, // Data Width`
48			`parameter ADDR_WIDTH = 1, // Address Width`
49			`parameter FIFO_DEPTH = 2 // FIFO DEPTH`
50
51			`)(`
52			`output [DATA_WIDTH-1:0] dout,`
53			`input rstn,`
54			`input clk,`
55			`input wr_en, // Write`
56			`input rd_en, // Read`
57			`input [DATA_WIDTH-1:0] din,`
58			`output full,`
59			`output empty`
60			`);`
61
62
63	18	dinesha	`reg [DATA_WIDTH-1:0] ram [FIFO_DEPTH-1:0];`
64	11	dinesha	`reg [ADDR_WIDTH-1:0] wptr; // write ptr`
65			`reg [ADDR_WIDTH-1:0] rptr; // write ptr`
66			`reg [ADDR_WIDTH:0] status_cnt; // status counter`
67	18	dinesha	`reg empty;`
68			`reg full;`
69	11	dinesha
70
71			`//-----------Code Start---------------------------`
72			`always @ (negedge rstn or posedge clk)`
73			`begin : WRITE_POINTER`
74			`if (rstn==1'b0) begin`
75			`wptr <= 0;`
76			`end else if (wr_en ) begin`
77			`wptr <= wptr + 1;`
78			`end`
79			`end`
80
81			`always @ (negedge rstn or posedge clk)`
82			`begin : READ_POINTER`
83			`if (rstn==1'b0) begin`
84			`rptr <= 0;`
85			`end else if (rd_en) begin`
86			`rptr <= rptr + 1;`
87			`end`
88			`end`
89
90			`always @ (negedge rstn or posedge clk)`
91			`begin : STATUS_COUNTER`
92			`if (rstn==1'b0) begin`
93			`status_cnt <= 0;`
94			`// Read but no write.`
95			`end else if (rd_en && (!wr_en) && (status_cnt != 0)) begin`
96			`status_cnt <= status_cnt - 1;`
97			`// Write but no read.`
98			`end else if (wr_en && (!rd_en) && (status_cnt != FIFO_DEPTH)) begin`
99			`status_cnt <= status_cnt + 1;`
100			`end`
101			`end`
102
103	18	dinesha	`// underflow is not handled`
104			`always @ (negedge rstn or posedge clk)`
105			`begin : EMPTY_FLAG`
106			`if (rstn==1'b0) begin`
107			`empty <= 1;`
108			`// Read but no write.`
109			`end else if (rd_en && (!wr_en) && (status_cnt == 1)) begin`
110			`empty <= 1;`
111			`// Write`
112			`end else if (wr_en) begin`
113			`empty <= 0;`
114			`end else if (status_cnt == 0) begin`
115			`empty <= 1;`
116			`end`
117			`end`
118	11	dinesha
119	18	dinesha	`// overflow is not handled`
120			`always @ (negedge rstn or posedge clk)`
121			`begin : FULL_FLAG`
122			`if (rstn==1'b0) begin`
123			`full <= 0;`
124			`// Write but no read.`
125			`end else if (wr_en && (!rd_en) && (status_cnt == (FIFO_DEPTH-1))) begin`
126			`full <= 1;`
127			`// Read`
128			`end else if (rd_en && (!wr_en) ) begin`
129			`full <= 0;`
130			`end else if (status_cnt == FIFO_DEPTH) begin`
131			`full <= 1;`
132			`end`
133			`end`
134	11	dinesha	`assign dout = ram[rptr];`
135
136			`always @ (posedge clk)`
137			`begin`
138			`if (wr_en) ram[wptr] <= din;`
139			`end`
140
141
142			`endmodule`

Browse

Tools

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [lib/] [sync_fifo.sv] - Blame information for rev 18