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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_clkgen.sv] - Blame information for rev 21

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SPI Clkgen  Module                                          ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////      This is SPI Master Clock Generation control logic.      ////
////      This logic also generate spi clock rise and fall pulse  ////
////      Basis assumption is master clock is 2x time spi clock   ////
////         1. spi fall pulse is used to transmit spi data       ////
////         2. spi rise pulse is used to received spi data       ////
////     SPI Master Top module                                    ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision:                                                   ////
////      0.1 - 16th Feb 2021, Dinesh A                           ////
////            Initial version                                   ////
////      0.2 - 24th Mar 2021, Dinesh A                           ////
////            1. Comments are added                             ////
////            2. RTL clean-up done and the output are registred ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module spim_clkgen
(
    input  logic                        clk,
    input  logic                        rstn,
    input  logic                        en,
    input  logic          [7:0]         cfg_sck_period,
    output logic                        spi_clk,
    output logic                        spi_fall,
    output logic                        spi_rise
);
 
        logic [7:0] sck_half_period;
        logic [7:0] clk_cnt;
 
    assign sck_half_period = {1'b0, cfg_sck_period[7:1]};
 
    // The first transition on the sck_toggle happens one SCK period
    // after en is asserted
    always @(posedge clk or negedge rstn) begin
        if(!rstn) begin
           clk_cnt    <= 'h1;
           spi_clk    <= 1'b1;
           spi_fall   <= 1'b0;
           spi_rise   <= 1'b0;
        end // if (!reset_n)
        else
        begin
           if(en)
           begin
              if(clk_cnt == sck_half_period)
              begin
                 spi_clk    <= 1'b0;
              end // if (clk_cnt == sck_half_period)
              else if(clk_cnt == cfg_sck_period) begin
                    spi_clk    <= 1'b1;
              end
           end else begin
              spi_clk    <= 1'b1;
           end // else: !if(en)
        end // else: !if(!reset_n)
    end // always @ (posedge clk or negedge reset_n)
 
    // Generate Free runnng spi_fall and rise pulse
    // after en is asserted
    always @(posedge clk or negedge rstn) begin
        if(!rstn) begin
           clk_cnt    <= 'h1;
           spi_fall   <= 1'b0;
           spi_rise   <= 1'b0;
        end // if (!reset_n)
        else
        begin
           if(clk_cnt == sck_half_period)
           begin
              spi_fall   <= 1'b0;
              spi_rise   <= 1'b1;
              clk_cnt    <= clk_cnt + 1'b1;
           end // if (clk_cnt == sck_half_period)
           else begin
              if(clk_cnt == cfg_sck_period)
              begin
                 spi_fall   <= 1'b1;
                 spi_rise   <= 1'b0;
                 clk_cnt    <= 'h1;
              end // if (clk_cnt == cfg_sck_period)
              else
              begin
                 clk_cnt    <= clk_cnt + 1'b1;
                 spi_fall   <= 1'b0;
                 spi_rise   <= 1'b0;
               end // else: !if(clk_cnt == cfg_sck_period)
           end // else: !if(clk_cnt == sck_half_period)
        end // else: !if(!reset_n)
    end // always @ (posedge clk or negedge reset_n)
 
endmodule

Line No.	Rev	Author	Line
1	18	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SPI Clkgen Module ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This is SPI Master Clock Generation control logic. ////`
10			`//// This logic also generate spi clock rise and fall pulse ////`
11			`//// Basis assumption is master clock is 2x time spi clock ////`
12			`//// 1. spi fall pulse is used to transmit spi data ////`
13			`//// 2. spi rise pulse is used to received spi data ////`
14			`//// SPI Master Top module ////`
15			`//// ////`
16			`//// To Do: ////`
17			`//// nothing ////`
18			`//// ////`
19			`//// Author(s): ////`
20			`//// - Dinesh Annayya, dinesha@opencores.org ////`
21			`//// ////`
22			`//// Revision: ////`
23			`//// 0.1 - 16th Feb 2021, Dinesh A ////`
24			`//// Initial version ////`
25			`//// 0.2 - 24th Mar 2021, Dinesh A ////`
26			`//// 1. Comments are added ////`
27			`//// 2. RTL clean-up done and the output are registred ////`
28			`//// ////`
29			`//////////////////////////////////////////////////////////////////////`
30			`//// ////`
31			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
32			`//// ////`
33			`//// This source file may be used and distributed without ////`
34			`//// restriction provided that this copyright statement is not ////`
35			`//// removed from the file and that any derivative work contains ////`
36			`//// the original copyright notice and the associated disclaimer. ////`
37			`//// ////`
38			`//// This source file is free software; you can redistribute it ////`
39			`//// and/or modify it under the terms of the GNU Lesser General ////`
40			`//// Public License as published by the Free Software Foundation; ////`
41			`//// either version 2.1 of the License, or (at your option) any ////`
42			`//// later version. ////`
43			`//// ////`
44			`//// This source is distributed in the hope that it will be ////`
45			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
46			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
47			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
48			`//// details. ////`
49			`//// ////`
50			`//// You should have received a copy of the GNU Lesser General ////`
51			`//// Public License along with this source; if not, download it ////`
52			`//// from http://www.opencores.org/lgpl.shtml ////`
53			`//// ////`
54			`//////////////////////////////////////////////////////////////////////`
55
56			`module spim_clkgen`
57			`(`
58			`input logic clk,`
59			`input logic rstn,`
60			`input logic en,`
61			`input logic [7:0] cfg_sck_period,`
62			`output logic spi_clk,`
63			`output logic spi_fall,`
64			`output logic spi_rise`
65			`);`
66
67			`logic [7:0] sck_half_period;`
68			`logic [7:0] clk_cnt;`
69
70			`assign sck_half_period = {1'b0, cfg_sck_period[7:1]};`
71
72			`// The first transition on the sck_toggle happens one SCK period`
73			`// after en is asserted`
74			`always @(posedge clk or negedge rstn) begin`
75			`if(!rstn) begin`
76			`clk_cnt <= 'h1;`
77			`spi_clk <= 1'b1;`
78			`spi_fall <= 1'b0;`
79			`spi_rise <= 1'b0;`
80			`end // if (!reset_n)`
81			`else`
82			`begin`
83			`if(en)`
84			`begin`
85			`if(clk_cnt == sck_half_period)`
86			`begin`
87			`spi_clk <= 1'b0;`
88			`end // if (clk_cnt == sck_half_period)`
89	21	dinesha	`else if(clk_cnt == cfg_sck_period) begin`
90	18	dinesha	`spi_clk <= 1'b1;`
91	21	dinesha	`end`
92			`end else begin`
93			`spi_clk <= 1'b1;`
94	18	dinesha	`end // else: !if(en)`
95			`end // else: !if(!reset_n)`
96			`end // always @ (posedge clk or negedge reset_n)`
97
98	21	dinesha	`// Generate Free runnng spi_fall and rise pulse`
99			`// after en is asserted`
100			`always @(posedge clk or negedge rstn) begin`
101			`if(!rstn) begin`
102			`clk_cnt <= 'h1;`
103			`spi_fall <= 1'b0;`
104			`spi_rise <= 1'b0;`
105			`end // if (!reset_n)`
106			`else`
107			`begin`
108			`if(clk_cnt == sck_half_period)`
109			`begin`
110			`spi_fall <= 1'b0;`
111			`spi_rise <= 1'b1;`
112			`clk_cnt <= clk_cnt + 1'b1;`
113			`end // if (clk_cnt == sck_half_period)`
114			`else begin`
115			`if(clk_cnt == cfg_sck_period)`
116			`begin`
117			`spi_fall <= 1'b1;`
118			`spi_rise <= 1'b0;`
119			`clk_cnt <= 'h1;`
120			`end // if (clk_cnt == cfg_sck_period)`
121			`else`
122			`begin`
123			`clk_cnt <= clk_cnt + 1'b1;`
124			`spi_fall <= 1'b0;`
125			`spi_rise <= 1'b0;`
126			`end // else: !if(clk_cnt == cfg_sck_period)`
127			`end // else: !if(clk_cnt == sck_half_period)`
128			`end // else: !if(!reset_n)`
129			`end // always @ (posedge clk or negedge reset_n)`
130
131	18	dinesha	`endmodule`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_clkgen.sv] - Blame information for rev 21