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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_ctrl.sv] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SPI CTRL I/F Module                                         ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision :                                                  ////
////     V.0  -  June 8, 2021                                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
module spim_ctrl
(
    input  logic                          clk,
    input  logic                          rstn,
    output logic                          eot,
 
    input  logic                    [7:0] spi_clk_div,
    input  logic                          spi_clk_div_valid,
    output logic                    [7:0] spi_status,
 
 
    input  logic                          spi_req,
    input  logic                   [31:0] spi_addr,
    input  logic                    [5:0] spi_addr_len,
    input  logic                   [7:0]  spi_cmd,
    input  logic                    [5:0] spi_cmd_len,
    input  logic                   [7:0]  spi_mode_cmd,
    input  logic                          spi_mode_cmd_enb,
    input  logic                    [3:0] spi_csreg,
    input  logic                   [15:0] spi_data_len,
    input  logic                   [15:0] spi_dummy_rd_len,
    input  logic                   [15:0] spi_dummy_wr_len,
    input  logic                          spi_swrst, //FIXME Not used at all
    input  logic                          spi_rd,
    input  logic                          spi_wr,
    input  logic                          spi_qrd,
    input  logic                          spi_qwr,
    input  logic                   [31:0] spi_wdata,
    output logic                   [31:0] spi_rdata,
    output logic                          spi_ack,
 
    output logic                          spi_clk,
    output logic                          spi_csn0,
    output logic                          spi_csn1,
    output logic                          spi_csn2,
    output logic                          spi_csn3,
    output logic                    [1:0] spi_mode,
    output logic                          spi_sdo0,
    output logic                          spi_sdo1,
    output logic                          spi_sdo2,
    output logic                          spi_sdo3,
    input  logic                          spi_sdi0,
    input  logic                          spi_sdi1,
    input  logic                          spi_sdi2,
    input  logic                          spi_sdi3,
    output logic                          spi_en_tx // Spi Direction control
);
 
 
parameter  SPI_STD     = 2'b00;
parameter  SPI_QUAD_TX = 2'b01;
parameter  SPI_QUAD_RX = 2'b10;
 
  logic spi_rise;
  logic spi_fall;
 
  logic spi_clock_en;
 
  logic spi_en_rx;
 
  logic [15:0] counter_tx;
  logic        counter_tx_valid;
  logic [15:0] counter_rx;
  logic        counter_rx_valid;
 
  logic [31:0] data_to_tx;
  logic        data_to_tx_valid;
  logic        data_to_tx_ready;
 
  logic en_quad;
  logic en_quad_int;
  logic do_tx; //FIXME NOT USED at all!!
  logic do_rx;
 
  logic tx_done;
  logic rx_done;
 
  logic [1:0] s_spi_mode;
 
  logic ctrl_data_valid;
 
  logic spi_cs;
 
  logic tx_clk_en;
  logic rx_clk_en;
  logic en_quad_in;
 
 
  enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;
 
  enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;
 
  assign en_quad = spi_qrd | spi_qwr | en_quad_int;
 
 
  assign en_quad_in = (s_spi_mode == SPI_STD) ? 1'b0 : 1'b1;
 
  spim_clkgen u_clkgen
  (
    .clk           ( clk               ),
    .rstn          ( rstn              ),
    .en            ( spi_clock_en      ),
    .cfg_sck_period( spi_clk_div       ),
    .spi_clk       ( spi_clk           ),
    .spi_fall      ( spi_fall          ),
    .spi_rise      ( spi_rise          )
  );
 
  spim_tx u_txreg
  (
    .clk            ( clk              ),
    .rstn           ( rstn             ),
    .en             ( spi_en_tx        ),
    .tx_edge        ( spi_fall         ),
    .tx_done        ( tx_done          ),
    .sdo0           ( spi_sdo0         ),
    .sdo1           ( spi_sdo1         ),
    .sdo2           ( spi_sdo2         ),
    .sdo3           ( spi_sdo3         ),
    .en_quad_in     ( en_quad_in       ),
    .counter_in     ( counter_tx       ),
    .txdata         ( data_to_tx       ),
    .data_valid     ( data_to_tx_valid ),
    .data_ready     (                  ),
    .clk_en_o       ( tx_clk_en        )
  );
 
  spim_rx u_rxreg
  (
    .clk            ( clk                    ),
    .rstn           ( rstn                   ),
    .en             ( spi_en_rx              ),
    .rx_edge        ( spi_rise               ),
    .rx_done        ( rx_done                ),
    .sdi0           ( spi_sdi0               ),
    .sdi1           ( spi_sdi1               ),
    .sdi2           ( spi_sdi2               ),
    .sdi3           ( spi_sdi3               ),
    .en_quad_in     ( en_quad_in             ),
    .counter_in     ( counter_rx             ),
    .counter_in_upd ( counter_rx_valid       ),
    .data           ( spi_rdata              ),
    .data_valid     (                        ),
    .data_ready     ( 1'b1                   ),
    .clk_en_o       ( rx_clk_en              )
  );
 
 
 
  always_comb
  begin
      data_to_tx       =  'h0;
      data_to_tx_valid = 1'b0;
 
      case(ctrl_data_mux)
          DATA_NULL:
          begin
              data_to_tx       =  '0;
              data_to_tx_valid = 1'b0;
          end
 
          DATA_EMPTY:
          begin
              data_to_tx       =  '0;
              data_to_tx_valid = 1'b1;
          end
 
          DATA_CMD:
          begin
              data_to_tx       = {spi_cmd,24'h0};
              data_to_tx_valid = ctrl_data_valid;
          end
          DATA_MODE:
          begin
              data_to_tx       = {spi_mode_cmd,24'h0};
              data_to_tx_valid = ctrl_data_valid;
          end
 
          DATA_ADDR:
          begin
              data_to_tx       = spi_addr;
              data_to_tx_valid = ctrl_data_valid;
          end
 
          DATA_FIFO:
          begin
             data_to_tx             = spi_wdata;
             data_to_tx_valid       = ctrl_data_valid;
          end
      endcase
  end
 
  always_comb
  begin
    spi_cs           = 1'b1;
    spi_clock_en     = 1'b0;
    counter_tx       =  '0;
    counter_tx_valid = 1'b0;
    counter_rx       =  '0;
    counter_rx_valid = 1'b0;
    state_next       = state;
    ctrl_data_mux    = DATA_NULL;
    ctrl_data_valid  = 1'b0;
    spi_en_rx        = 1'b0;
    spi_en_tx        = 1'b0;
    spi_status       =  '0;
    s_spi_mode       = SPI_QUAD_RX;
    eot              = 1'b0;
    case(state)
      IDLE:
      begin
        spi_status[0] = 1'b1;
        s_spi_mode = SPI_QUAD_RX;
        if (spi_req)
        begin
          spi_cs       = 1'b0;
          spi_clock_en = 1'b1;
 
          if (spi_cmd_len != 0)
          begin
//            s_spi_mode = (spi_qrd | spi_qwr) ? `SPI_QUAD_TX : `SPI_STD;
            s_spi_mode       = SPI_STD; // COMMAND is always Standard Mode ?
            counter_tx       = {8'h0,spi_cmd_len};
            counter_tx_valid = 1'b1;
            ctrl_data_mux    = DATA_CMD;
            ctrl_data_valid  = 1'b1;
            spi_en_tx        = 1'b1;
            state_next       = CMD;
          end
          else if (spi_addr_len != 0)
          begin
            s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
            counter_tx       = {8'h0,spi_addr_len};
            counter_tx_valid = 1'b1;
            ctrl_data_mux    = DATA_ADDR;
            ctrl_data_valid  = 1'b1;
            spi_en_tx        = 1'b1;
            state_next       = ADDR;
          end
          else if (spi_mode_cmd_enb != 0)
          begin
            s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
            counter_tx       = {8'h0,8'h8};
            counter_tx_valid = 1'b1;
            ctrl_data_mux    = DATA_MODE;
            ctrl_data_valid  = 1'b1;
            spi_en_tx        = 1'b1;
            state_next       = MODE;
          end
          else if (spi_data_len != 0)
          begin
             if (spi_rd || spi_qrd)
             begin
                s_spi_mode = (spi_qrd) ? SPI_QUAD_RX : SPI_STD;
                if(spi_dummy_rd_len != 0)
                begin
                  counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
                  counter_tx_valid = 1'b1;
                  spi_en_tx        = 1'b1;
                  ctrl_data_mux    = DATA_EMPTY;
                  state_next       = DUMMY;
                end
                else
                begin
                   counter_rx       = spi_data_len;
                   counter_rx_valid = 1'b1;
                   spi_en_rx        = 1'b1;
                   state_next       = DATA_RX;
                end
             end
             else
             begin
                s_spi_mode = (spi_qwr) ? SPI_QUAD_TX : SPI_STD;
                if(spi_dummy_wr_len != 0)
                begin
                   counter_tx       = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
                   counter_tx_valid = 1'b1;
                   ctrl_data_mux    = DATA_EMPTY;
                   spi_en_tx        = 1'b1;
                   state_next       = DUMMY;
                end
                else
                begin
                   counter_tx       = spi_data_len;
                   counter_tx_valid = 1'b1;
                   ctrl_data_mux    = DATA_FIFO;
                   ctrl_data_valid  = 1'b0;
                   spi_en_tx        = 1'b1;
                   state_next       = DATA_TX;
                end
             end
          end
        end
        else
        begin
          spi_cs = 1'b1;
          state_next = IDLE;
        end
      end
 
      CMD:
      begin
        spi_status[1] = 1'b1;
        spi_cs = 1'b0;
        spi_clock_en = 1'b1;
//      s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
        s_spi_mode = SPI_STD; // Command is always Standard Mode ?
        if (tx_done)
        begin
          if (spi_addr_len != 0)
          begin
            s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
            counter_tx       = {8'h0,spi_addr_len};
            counter_tx_valid = 1'b1;
            ctrl_data_mux    = DATA_ADDR;
            ctrl_data_valid  = 1'b1;
            spi_en_tx        = 1'b1;
            state_next       = ADDR;
          end
          else if (spi_mode_cmd_enb != 0)
          begin
            s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
            counter_tx       = {8'h0,8'h8};
            counter_tx_valid = 1'b1;
            ctrl_data_mux    = DATA_MODE;
            ctrl_data_valid  = 1'b1;
            spi_en_tx        = 1'b1;
            state_next       = MODE;
          end
          else if (spi_data_len != 0)
          begin
            if (do_rx)
            begin
              s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
              if(spi_dummy_rd_len != 0)
              begin
                counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
                counter_tx_valid = 1'b1;
                spi_en_tx        = 1'b1;
                ctrl_data_mux    = DATA_EMPTY;
                state_next       = DUMMY;
              end
              else
              begin
                counter_rx       = spi_data_len;
                counter_rx_valid = 1'b1;
                spi_en_rx        = 1'b1;
                state_next       = DATA_RX;
              end
            end
            else
            begin
              s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
              if(spi_dummy_wr_len != 0)
              begin
                counter_tx       = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
                counter_tx_valid = 1'b1;
                ctrl_data_mux    = DATA_EMPTY;
                spi_en_tx        = 1'b1;
                state_next       = DUMMY;
              end
              else
              begin
                counter_tx       = spi_data_len;
                counter_tx_valid = 1'b1;
                ctrl_data_mux    = DATA_FIFO;
                ctrl_data_valid  = 1'b1;
                spi_en_tx        = 1'b1;
                state_next       = DATA_TX;
              end
            end
          end
          else
          begin
            spi_en_tx  = 1'b1;
            state_next = WAIT_EDGE;
          end
        end
        else
        begin
          spi_en_tx  = 1'b1;
          state_next = CMD;
        end
      end
 
      ADDR:
      begin
        spi_en_tx     = 1'b1;
        spi_status[2] = 1'b1;
        spi_cs        = 1'b0;
        spi_clock_en  = 1'b1;
        s_spi_mode    = (en_quad) ? SPI_QUAD_TX : SPI_STD;
 
        if (tx_done)
        begin
          if (spi_mode_cmd_enb != 0)
          begin
            s_spi_mode = (spi_qrd | spi_qwr) ? SPI_QUAD_TX : SPI_STD;
            counter_tx       = {8'h0,8'h8};
            counter_tx_valid = 1'b1;
            ctrl_data_mux    = DATA_MODE;
            ctrl_data_valid  = 1'b1;
            spi_en_tx        = 1'b1;
            state_next       = MODE;
          end
          else if (spi_data_len != 0)
          begin
            if (do_rx)
            begin
              s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
              if(spi_dummy_rd_len != 0)
              begin
                counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
                counter_tx_valid = 1'b1;
                spi_en_tx        = 1'b1;
                ctrl_data_mux    = DATA_EMPTY;
                state_next       = DUMMY;
              end
              else
              begin
                counter_rx       = spi_data_len;
                counter_rx_valid = 1'b1;
                spi_en_rx        = 1'b1;
                state_next       = DATA_RX;
              end
            end
            else
            begin
              s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
              spi_en_tx  = 1'b1;
 
              if(spi_dummy_wr_len != 0) begin
                counter_tx       = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
                counter_tx_valid = 1'b1;
                ctrl_data_mux    = DATA_EMPTY;
                state_next       = DUMMY;
              end else begin
                counter_tx       = spi_data_len;
                counter_tx_valid = 1'b1;
                ctrl_data_mux    = DATA_FIFO;
                ctrl_data_valid  = 1'b1;
                state_next       = DATA_TX;
              end
            end
          end
          else
          begin
            state_next = WAIT_EDGE;
          end
        end
      end
 
      MODE:
      begin
        spi_en_tx     = 1'b1;
        spi_status[3] = 1'b1;
        spi_cs        = 1'b0;
        spi_clock_en  = 1'b1;
        s_spi_mode    = (en_quad) ? SPI_QUAD_TX : SPI_STD;
        if (tx_done)
        begin
          if (spi_data_len != 0)
          begin
            if (do_rx)
            begin
              s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;
              if(spi_dummy_rd_len != 0)
              begin
                counter_tx       = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;
                counter_tx_valid = 1'b1;
                spi_en_tx        = 1'b1;
                ctrl_data_mux    = DATA_EMPTY;
                state_next       = DUMMY;
              end
              else
              begin
                counter_rx       = spi_data_len;
                counter_rx_valid = 1'b1;
                spi_en_rx        = 1'b1;
                state_next       = DATA_RX;
              end
            end
            else
            begin
              s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;
              spi_en_tx  = 1'b1;
 
              if(spi_dummy_wr_len != 0) begin
                counter_tx       = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;
                counter_tx_valid = 1'b1;
                ctrl_data_mux    = DATA_EMPTY;
                state_next       = DUMMY;
              end else begin
                counter_tx       = spi_data_len;
                counter_tx_valid = 1'b1;
                ctrl_data_mux    = DATA_FIFO;
                ctrl_data_valid  = 1'b1;
                state_next       = DATA_TX;
              end
            end
          end
          else
          begin
            state_next = WAIT_EDGE;
          end
        end
      end
 
      DUMMY:
      begin
        spi_en_tx     = 1'b1;
        spi_status[4] = 1'b1;
        spi_cs        = 1'b0;
        spi_clock_en  = 1'b1;
        s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
 
        if (tx_done) begin
          if (spi_data_len != 0) begin
            if (do_rx) begin
              counter_rx       = spi_data_len;
              counter_rx_valid = 1'b1;
              spi_en_rx        = 1'b1;
              state_next       = DATA_RX;
            end else begin
              counter_tx       = spi_data_len;
              counter_tx_valid = 1'b1;
              s_spi_mode       = (en_quad) ? SPI_QUAD_TX : SPI_STD;
 
              spi_clock_en     = tx_clk_en;
              spi_en_tx        = 1'b1;
              state_next       = DATA_TX;
            end
          end
          else
          begin
            eot        = 1'b1;
            state_next = WAIT_EDGE;
          end
        end
        else
        begin
          ctrl_data_mux = DATA_EMPTY;
          spi_en_tx     = 1'b1;
          state_next    = DUMMY;
        end
      end
 
      DATA_TX:
      begin
        spi_status[5]    = 1'b1;
        spi_cs           = 1'b0;
        spi_clock_en     = tx_clk_en;
        ctrl_data_mux    = DATA_FIFO;
        ctrl_data_valid  = 1'b1;
        spi_en_tx        = 1'b1;
        s_spi_mode       = (en_quad) ? SPI_QUAD_TX : SPI_STD;
 
        if (tx_done) begin
          eot          = 1'b1;
          state_next   = WAIT_EDGE;
          spi_clock_en = 1'b0;
        end else begin
          state_next = DATA_TX;
        end
      end
 
      DATA_RX:
      begin
        spi_status[6] = 1'b1;
        spi_cs        = 1'b0;
        spi_clock_en  = rx_clk_en;
        s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
 
        if (rx_done) begin
          state_next = WAIT_EDGE;
        end else begin
          spi_en_rx  = 1'b1;
          state_next = DATA_RX;
        end
      end
      WAIT_EDGE:
      begin
        spi_status[7] = 1'b1;
        spi_cs        = 1'b0;
        spi_clock_en  = 1'b0;
        s_spi_mode    = (en_quad) ? SPI_QUAD_RX : SPI_STD;
        eot           = 1'b1;
        state_next    = IDLE;
      end
    endcase
  end
 
assign  spi_ack = ((spi_req ==1) && (state_next == WAIT_EDGE)) ? 1'b1 : 1'b0;
 
 
  always_ff @(posedge clk, negedge rstn)
  begin
    if (rstn == 1'b0)
    begin
      state       <= IDLE;
      en_quad_int <= 1'b0;
      do_rx       <= 1'b0;
      do_tx       <= 1'b0;
      spi_mode    <= SPI_QUAD_RX;
    end
    else
    begin
       state <= state_next;
       spi_mode <= s_spi_mode;
      if (spi_qrd || spi_qwr)
        en_quad_int <= 1'b1;
      else if (state_next == IDLE)
        en_quad_int <= 1'b0;
 
      if (spi_rd || spi_qrd)
      begin
        do_rx <= 1'b1;
        do_tx <= 1'b0;
      end
      else if (spi_wr || spi_qwr)
      begin
        do_rx <= 1'b0;
        do_tx <= 1'b1;
      end
      else if (state_next == IDLE)
      begin
        do_rx <= 1'b0;
        do_tx <= 1'b0;
      end
    end
  end
 
  assign spi_csn0 = ~spi_csreg[0] | spi_cs;
  assign spi_csn1 = ~spi_csreg[1] | spi_cs;
  assign spi_csn2 = ~spi_csreg[2] | spi_cs;
  assign spi_csn3 = ~spi_csreg[3] | spi_cs;
 
endmodule
 

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_ctrl.sv] - Blame information for rev 18

Line No.	Rev	Author	Line
1	18	dinesha
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// SPI CTRL I/F Module ////`
5			`//// ////`
6			`//// This file is part of the YIFive cores project ////`
7			`//// http://www.opencores.org/cores/yifive/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : ////`
18			`//// V.0 - June 8, 2021 ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46			`module spim_ctrl`
47			`(`
48			`input logic clk,`
49			`input logic rstn,`
50			`output logic eot,`
51
52			`input logic [7:0] spi_clk_div,`
53			`input logic spi_clk_div_valid,`
54			`output logic [7:0] spi_status,`
55
56
57			`input logic spi_req,`
58			`input logic [31:0] spi_addr,`
59			`input logic [5:0] spi_addr_len,`
60			`input logic [7:0] spi_cmd,`
61			`input logic [5:0] spi_cmd_len,`
62			`input logic [7:0] spi_mode_cmd,`
63			`input logic spi_mode_cmd_enb,`
64			`input logic [3:0] spi_csreg,`
65			`input logic [15:0] spi_data_len,`
66			`input logic [15:0] spi_dummy_rd_len,`
67			`input logic [15:0] spi_dummy_wr_len,`
68			`input logic spi_swrst, //FIXME Not used at all`
69			`input logic spi_rd,`
70			`input logic spi_wr,`
71			`input logic spi_qrd,`
72			`input logic spi_qwr,`
73			`input logic [31:0] spi_wdata,`
74			`output logic [31:0] spi_rdata,`
75			`output logic spi_ack,`
76
77			`output logic spi_clk,`
78			`output logic spi_csn0,`
79			`output logic spi_csn1,`
80			`output logic spi_csn2,`
81			`output logic spi_csn3,`
82			`output logic [1:0] spi_mode,`
83			`output logic spi_sdo0,`
84			`output logic spi_sdo1,`
85			`output logic spi_sdo2,`
86			`output logic spi_sdo3,`
87			`input logic spi_sdi0,`
88			`input logic spi_sdi1,`
89			`input logic spi_sdi2,`
90			`input logic spi_sdi3,`
91			`output logic spi_en_tx // Spi Direction control`
92			`);`
93
94
95			`parameter SPI_STD = 2'b00;`
96			`parameter SPI_QUAD_TX = 2'b01;`
97			`parameter SPI_QUAD_RX = 2'b10;`
98
99			`logic spi_rise;`
100			`logic spi_fall;`
101
102			`logic spi_clock_en;`
103
104			`logic spi_en_rx;`
105
106			`logic [15:0] counter_tx;`
107			`logic counter_tx_valid;`
108			`logic [15:0] counter_rx;`
109			`logic counter_rx_valid;`
110
111			`logic [31:0] data_to_tx;`
112			`logic data_to_tx_valid;`
113			`logic data_to_tx_ready;`
114
115			`logic en_quad;`
116			`logic en_quad_int;`
117			`logic do_tx; //FIXME NOT USED at all!!`
118			`logic do_rx;`
119
120			`logic tx_done;`
121			`logic rx_done;`
122
123			`logic [1:0] s_spi_mode;`
124
125			`logic ctrl_data_valid;`
126
127			`logic spi_cs;`
128
129			`logic tx_clk_en;`
130			`logic rx_clk_en;`
131			`logic en_quad_in;`
132
133
134			`enum logic [2:0] {DATA_NULL,DATA_EMPTY,DATA_CMD,DATA_ADDR,DATA_MODE,DATA_FIFO} ctrl_data_mux;`
135
136			`enum logic [4:0] {IDLE,CMD,ADDR,MODE,DUMMY,DATA_TX,DATA_RX,WAIT_EDGE} state,state_next;`
137
138			`assign en_quad = spi_qrd \| spi_qwr \| en_quad_int;`
139
140
141			`assign en_quad_in = (s_spi_mode == SPI_STD) ? 1'b0 : 1'b1;`
142
143			`spim_clkgen u_clkgen`
144			`(`
145			`.clk ( clk ),`
146			`.rstn ( rstn ),`
147			`.en ( spi_clock_en ),`
148			`.cfg_sck_period( spi_clk_div ),`
149			`.spi_clk ( spi_clk ),`
150			`.spi_fall ( spi_fall ),`
151			`.spi_rise ( spi_rise )`
152			`);`
153
154			`spim_tx u_txreg`
155			`(`
156			`.clk ( clk ),`
157			`.rstn ( rstn ),`
158			`.en ( spi_en_tx ),`
159			`.tx_edge ( spi_fall ),`
160			`.tx_done ( tx_done ),`
161			`.sdo0 ( spi_sdo0 ),`
162			`.sdo1 ( spi_sdo1 ),`
163			`.sdo2 ( spi_sdo2 ),`
164			`.sdo3 ( spi_sdo3 ),`
165			`.en_quad_in ( en_quad_in ),`
166			`.counter_in ( counter_tx ),`
167			`.txdata ( data_to_tx ),`
168			`.data_valid ( data_to_tx_valid ),`
169			`.data_ready ( ),`
170			`.clk_en_o ( tx_clk_en )`
171			`);`
172
173			`spim_rx u_rxreg`
174			`(`
175			`.clk ( clk ),`
176			`.rstn ( rstn ),`
177			`.en ( spi_en_rx ),`
178			`.rx_edge ( spi_rise ),`
179			`.rx_done ( rx_done ),`
180			`.sdi0 ( spi_sdi0 ),`
181			`.sdi1 ( spi_sdi1 ),`
182			`.sdi2 ( spi_sdi2 ),`
183			`.sdi3 ( spi_sdi3 ),`
184			`.en_quad_in ( en_quad_in ),`
185			`.counter_in ( counter_rx ),`
186			`.counter_in_upd ( counter_rx_valid ),`
187			`.data ( spi_rdata ),`
188			`.data_valid ( ),`
189			`.data_ready ( 1'b1 ),`
190			`.clk_en_o ( rx_clk_en )`
191			`);`
192
193
194
195			`always_comb`
196			`begin`
197			`data_to_tx = 'h0;`
198			`data_to_tx_valid = 1'b0;`
199
200			`case(ctrl_data_mux)`
201			`DATA_NULL:`
202			`begin`
203			`data_to_tx = '0;`
204			`data_to_tx_valid = 1'b0;`
205			`end`
206
207			`DATA_EMPTY:`
208			`begin`
209			`data_to_tx = '0;`
210			`data_to_tx_valid = 1'b1;`
211			`end`
212
213			`DATA_CMD:`
214			`begin`
215			`data_to_tx = {spi_cmd,24'h0};`
216			`data_to_tx_valid = ctrl_data_valid;`
217			`end`
218			`DATA_MODE:`
219			`begin`
220			`data_to_tx = {spi_mode_cmd,24'h0};`
221			`data_to_tx_valid = ctrl_data_valid;`
222			`end`
223
224			`DATA_ADDR:`
225			`begin`
226			`data_to_tx = spi_addr;`
227			`data_to_tx_valid = ctrl_data_valid;`
228			`end`
229
230			`DATA_FIFO:`
231			`begin`
232			`data_to_tx = spi_wdata;`
233			`data_to_tx_valid = ctrl_data_valid;`
234			`end`
235			`endcase`
236			`end`
237
238			`always_comb`
239			`begin`
240			`spi_cs = 1'b1;`
241			`spi_clock_en = 1'b0;`
242			`counter_tx = '0;`
243			`counter_tx_valid = 1'b0;`
244			`counter_rx = '0;`
245			`counter_rx_valid = 1'b0;`
246			`state_next = state;`
247			`ctrl_data_mux = DATA_NULL;`
248			`ctrl_data_valid = 1'b0;`
249			`spi_en_rx = 1'b0;`
250			`spi_en_tx = 1'b0;`
251			`spi_status = '0;`
252			`s_spi_mode = SPI_QUAD_RX;`
253			`eot = 1'b0;`
254			`case(state)`
255			`IDLE:`
256			`begin`
257			`spi_status[0] = 1'b1;`
258			`s_spi_mode = SPI_QUAD_RX;`
259			`if (spi_req)`
260			`begin`
261			`spi_cs = 1'b0;`
262			`spi_clock_en = 1'b1;`
263
264			`if (spi_cmd_len != 0)`
265			`begin`
266			// s_spi_mode = (spi_qrd \| spi_qwr) ? `SPI_QUAD_TX : `SPI_STD;
267			`s_spi_mode = SPI_STD; // COMMAND is always Standard Mode ?`
268			`counter_tx = {8'h0,spi_cmd_len};`
269			`counter_tx_valid = 1'b1;`
270			`ctrl_data_mux = DATA_CMD;`
271			`ctrl_data_valid = 1'b1;`
272			`spi_en_tx = 1'b1;`
273			`state_next = CMD;`
274			`end`
275			`else if (spi_addr_len != 0)`
276			`begin`
277			`s_spi_mode = (spi_qrd \| spi_qwr) ? SPI_QUAD_TX : SPI_STD;`
278			`counter_tx = {8'h0,spi_addr_len};`
279			`counter_tx_valid = 1'b1;`
280			`ctrl_data_mux = DATA_ADDR;`
281			`ctrl_data_valid = 1'b1;`
282			`spi_en_tx = 1'b1;`
283			`state_next = ADDR;`
284			`end`
285			`else if (spi_mode_cmd_enb != 0)`
286			`begin`
287			`s_spi_mode = (spi_qrd \| spi_qwr) ? SPI_QUAD_TX : SPI_STD;`
288			`counter_tx = {8'h0,8'h8};`
289			`counter_tx_valid = 1'b1;`
290			`ctrl_data_mux = DATA_MODE;`
291			`ctrl_data_valid = 1'b1;`
292			`spi_en_tx = 1'b1;`
293			`state_next = MODE;`
294			`end`
295			`else if (spi_data_len != 0)`
296			`begin`
297			`if (spi_rd \|\| spi_qrd)`
298			`begin`
299			`s_spi_mode = (spi_qrd) ? SPI_QUAD_RX : SPI_STD;`
300			`if(spi_dummy_rd_len != 0)`
301			`begin`
302			`counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;`
303			`counter_tx_valid = 1'b1;`
304			`spi_en_tx = 1'b1;`
305			`ctrl_data_mux = DATA_EMPTY;`
306			`state_next = DUMMY;`
307			`end`
308			`else`
309			`begin`
310			`counter_rx = spi_data_len;`
311			`counter_rx_valid = 1'b1;`
312			`spi_en_rx = 1'b1;`
313			`state_next = DATA_RX;`
314			`end`
315			`end`
316			`else`
317			`begin`
318			`s_spi_mode = (spi_qwr) ? SPI_QUAD_TX : SPI_STD;`
319			`if(spi_dummy_wr_len != 0)`
320			`begin`
321			`counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;`
322			`counter_tx_valid = 1'b1;`
323			`ctrl_data_mux = DATA_EMPTY;`
324			`spi_en_tx = 1'b1;`
325			`state_next = DUMMY;`
326			`end`
327			`else`
328			`begin`
329			`counter_tx = spi_data_len;`
330			`counter_tx_valid = 1'b1;`
331			`ctrl_data_mux = DATA_FIFO;`
332			`ctrl_data_valid = 1'b0;`
333			`spi_en_tx = 1'b1;`
334			`state_next = DATA_TX;`
335			`end`
336			`end`
337			`end`
338			`end`
339			`else`
340			`begin`
341			`spi_cs = 1'b1;`
342			`state_next = IDLE;`
343			`end`
344			`end`
345
346			`CMD:`
347			`begin`
348			`spi_status[1] = 1'b1;`
349			`spi_cs = 1'b0;`
350			`spi_clock_en = 1'b1;`
351			`// s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
352			`s_spi_mode = SPI_STD; // Command is always Standard Mode ?`
353			`if (tx_done)`
354			`begin`
355			`if (spi_addr_len != 0)`
356			`begin`
357			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
358			`counter_tx = {8'h0,spi_addr_len};`
359			`counter_tx_valid = 1'b1;`
360			`ctrl_data_mux = DATA_ADDR;`
361			`ctrl_data_valid = 1'b1;`
362			`spi_en_tx = 1'b1;`
363			`state_next = ADDR;`
364			`end`
365			`else if (spi_mode_cmd_enb != 0)`
366			`begin`
367			`s_spi_mode = (spi_qrd \| spi_qwr) ? SPI_QUAD_TX : SPI_STD;`
368			`counter_tx = {8'h0,8'h8};`
369			`counter_tx_valid = 1'b1;`
370			`ctrl_data_mux = DATA_MODE;`
371			`ctrl_data_valid = 1'b1;`
372			`spi_en_tx = 1'b1;`
373			`state_next = MODE;`
374			`end`
375			`else if (spi_data_len != 0)`
376			`begin`
377			`if (do_rx)`
378			`begin`
379			`s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;`
380			`if(spi_dummy_rd_len != 0)`
381			`begin`
382			`counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;`
383			`counter_tx_valid = 1'b1;`
384			`spi_en_tx = 1'b1;`
385			`ctrl_data_mux = DATA_EMPTY;`
386			`state_next = DUMMY;`
387			`end`
388			`else`
389			`begin`
390			`counter_rx = spi_data_len;`
391			`counter_rx_valid = 1'b1;`
392			`spi_en_rx = 1'b1;`
393			`state_next = DATA_RX;`
394			`end`
395			`end`
396			`else`
397			`begin`
398			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
399			`if(spi_dummy_wr_len != 0)`
400			`begin`
401			`counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;`
402			`counter_tx_valid = 1'b1;`
403			`ctrl_data_mux = DATA_EMPTY;`
404			`spi_en_tx = 1'b1;`
405			`state_next = DUMMY;`
406			`end`
407			`else`
408			`begin`
409			`counter_tx = spi_data_len;`
410			`counter_tx_valid = 1'b1;`
411			`ctrl_data_mux = DATA_FIFO;`
412			`ctrl_data_valid = 1'b1;`
413			`spi_en_tx = 1'b1;`
414			`state_next = DATA_TX;`
415			`end`
416			`end`
417			`end`
418			`else`
419			`begin`
420			`spi_en_tx = 1'b1;`
421			`state_next = WAIT_EDGE;`
422			`end`
423			`end`
424			`else`
425			`begin`
426			`spi_en_tx = 1'b1;`
427			`state_next = CMD;`
428			`end`
429			`end`
430
431			`ADDR:`
432			`begin`
433			`spi_en_tx = 1'b1;`
434			`spi_status[2] = 1'b1;`
435			`spi_cs = 1'b0;`
436			`spi_clock_en = 1'b1;`
437			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
438
439			`if (tx_done)`
440			`begin`
441			`if (spi_mode_cmd_enb != 0)`
442			`begin`
443			`s_spi_mode = (spi_qrd \| spi_qwr) ? SPI_QUAD_TX : SPI_STD;`
444			`counter_tx = {8'h0,8'h8};`
445			`counter_tx_valid = 1'b1;`
446			`ctrl_data_mux = DATA_MODE;`
447			`ctrl_data_valid = 1'b1;`
448			`spi_en_tx = 1'b1;`
449			`state_next = MODE;`
450			`end`
451			`else if (spi_data_len != 0)`
452			`begin`
453			`if (do_rx)`
454			`begin`
455			`s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;`
456			`if(spi_dummy_rd_len != 0)`
457			`begin`
458			`counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;`
459			`counter_tx_valid = 1'b1;`
460			`spi_en_tx = 1'b1;`
461			`ctrl_data_mux = DATA_EMPTY;`
462			`state_next = DUMMY;`
463			`end`
464			`else`
465			`begin`
466			`counter_rx = spi_data_len;`
467			`counter_rx_valid = 1'b1;`
468			`spi_en_rx = 1'b1;`
469			`state_next = DATA_RX;`
470			`end`
471			`end`
472			`else`
473			`begin`
474			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
475			`spi_en_tx = 1'b1;`
476
477			`if(spi_dummy_wr_len != 0) begin`
478			`counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;`
479			`counter_tx_valid = 1'b1;`
480			`ctrl_data_mux = DATA_EMPTY;`
481			`state_next = DUMMY;`
482			`end else begin`
483			`counter_tx = spi_data_len;`
484			`counter_tx_valid = 1'b1;`
485			`ctrl_data_mux = DATA_FIFO;`
486			`ctrl_data_valid = 1'b1;`
487			`state_next = DATA_TX;`
488			`end`
489			`end`
490			`end`
491			`else`
492			`begin`
493			`state_next = WAIT_EDGE;`
494			`end`
495			`end`
496			`end`
497
498			`MODE:`
499			`begin`
500			`spi_en_tx = 1'b1;`
501			`spi_status[3] = 1'b1;`
502			`spi_cs = 1'b0;`
503			`spi_clock_en = 1'b1;`
504			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
505			`if (tx_done)`
506			`begin`
507			`if (spi_data_len != 0)`
508			`begin`
509			`if (do_rx)`
510			`begin`
511			`s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;`
512			`if(spi_dummy_rd_len != 0)`
513			`begin`
514			`counter_tx = en_quad ? {2'b00,spi_dummy_rd_len[13:0]} : spi_dummy_rd_len;`
515			`counter_tx_valid = 1'b1;`
516			`spi_en_tx = 1'b1;`
517			`ctrl_data_mux = DATA_EMPTY;`
518			`state_next = DUMMY;`
519			`end`
520			`else`
521			`begin`
522			`counter_rx = spi_data_len;`
523			`counter_rx_valid = 1'b1;`
524			`spi_en_rx = 1'b1;`
525			`state_next = DATA_RX;`
526			`end`
527			`end`
528			`else`
529			`begin`
530			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
531			`spi_en_tx = 1'b1;`
532
533			`if(spi_dummy_wr_len != 0) begin`
534			`counter_tx = en_quad ? {2'b00,spi_dummy_wr_len[13:0]} : spi_dummy_wr_len;`
535			`counter_tx_valid = 1'b1;`
536			`ctrl_data_mux = DATA_EMPTY;`
537			`state_next = DUMMY;`
538			`end else begin`
539			`counter_tx = spi_data_len;`
540			`counter_tx_valid = 1'b1;`
541			`ctrl_data_mux = DATA_FIFO;`
542			`ctrl_data_valid = 1'b1;`
543			`state_next = DATA_TX;`
544			`end`
545			`end`
546			`end`
547			`else`
548			`begin`
549			`state_next = WAIT_EDGE;`
550			`end`
551			`end`
552			`end`
553
554			`DUMMY:`
555			`begin`
556			`spi_en_tx = 1'b1;`
557			`spi_status[4] = 1'b1;`
558			`spi_cs = 1'b0;`
559			`spi_clock_en = 1'b1;`
560			`s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;`
561
562			`if (tx_done) begin`
563			`if (spi_data_len != 0) begin`
564			`if (do_rx) begin`
565			`counter_rx = spi_data_len;`
566			`counter_rx_valid = 1'b1;`
567			`spi_en_rx = 1'b1;`
568			`state_next = DATA_RX;`
569			`end else begin`
570			`counter_tx = spi_data_len;`
571			`counter_tx_valid = 1'b1;`
572			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
573
574			`spi_clock_en = tx_clk_en;`
575			`spi_en_tx = 1'b1;`
576			`state_next = DATA_TX;`
577			`end`
578			`end`
579			`else`
580			`begin`
581			`eot = 1'b1;`
582			`state_next = WAIT_EDGE;`
583			`end`
584			`end`
585			`else`
586			`begin`
587			`ctrl_data_mux = DATA_EMPTY;`
588			`spi_en_tx = 1'b1;`
589			`state_next = DUMMY;`
590			`end`
591			`end`
592
593			`DATA_TX:`
594			`begin`
595			`spi_status[5] = 1'b1;`
596			`spi_cs = 1'b0;`
597			`spi_clock_en = tx_clk_en;`
598			`ctrl_data_mux = DATA_FIFO;`
599			`ctrl_data_valid = 1'b1;`
600			`spi_en_tx = 1'b1;`
601			`s_spi_mode = (en_quad) ? SPI_QUAD_TX : SPI_STD;`
602
603			`if (tx_done) begin`
604			`eot = 1'b1;`
605			`state_next = WAIT_EDGE;`
606			`spi_clock_en = 1'b0;`
607			`end else begin`
608			`state_next = DATA_TX;`
609			`end`
610			`end`
611
612			`DATA_RX:`
613			`begin`
614			`spi_status[6] = 1'b1;`
615			`spi_cs = 1'b0;`
616			`spi_clock_en = rx_clk_en;`
617			`s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;`
618
619			`if (rx_done) begin`
620			`state_next = WAIT_EDGE;`
621			`end else begin`
622			`spi_en_rx = 1'b1;`
623			`state_next = DATA_RX;`
624			`end`
625			`end`
626			`WAIT_EDGE:`
627			`begin`
628			`spi_status[7] = 1'b1;`
629			`spi_cs = 1'b0;`
630			`spi_clock_en = 1'b0;`
631			`s_spi_mode = (en_quad) ? SPI_QUAD_RX : SPI_STD;`
632			`eot = 1'b1;`
633			`state_next = IDLE;`
634			`end`
635			`endcase`
636			`end`
637
638			`assign spi_ack = ((spi_req ==1) && (state_next == WAIT_EDGE)) ? 1'b1 : 1'b0;`
639
640
641			`always_ff @(posedge clk, negedge rstn)`
642			`begin`
643			`if (rstn == 1'b0)`
644			`begin`
645			`state <= IDLE;`
646			`en_quad_int <= 1'b0;`
647			`do_rx <= 1'b0;`
648			`do_tx <= 1'b0;`
649			`spi_mode <= SPI_QUAD_RX;`
650			`end`
651			`else`
652			`begin`
653			`state <= state_next;`
654			`spi_mode <= s_spi_mode;`
655			`if (spi_qrd \|\| spi_qwr)`
656			`en_quad_int <= 1'b1;`
657			`else if (state_next == IDLE)`
658			`en_quad_int <= 1'b0;`
659
660			`if (spi_rd \|\| spi_qrd)`
661			`begin`
662			`do_rx <= 1'b1;`
663			`do_tx <= 1'b0;`
664			`end`
665			`else if (spi_wr \|\| spi_qwr)`
666			`begin`
667			`do_rx <= 1'b0;`
668			`do_tx <= 1'b1;`
669			`end`
670			`else if (state_next == IDLE)`
671			`begin`
672			`do_rx <= 1'b0;`
673			`do_tx <= 1'b0;`
674			`end`
675			`end`
676			`end`
677
678			`assign spi_csn0 = ~spi_csreg[0] \| spi_cs;`
679			`assign spi_csn1 = ~spi_csreg[1] \| spi_cs;`
680			`assign spi_csn2 = ~spi_csreg[2] \| spi_cs;`
681			`assign spi_csn3 = ~spi_csreg[3] \| spi_cs;`
682
683			`endmodule`
684