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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  YiFive cores common library Module                          ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////     Sync Fifo with full and empty                            ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision : June 7, 2021                                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module spim_fifo #(
      parameter  DATA_WIDTH  = 32, // Data Width
      parameter  ADDR_WIDTH   = 1, // Address Width
      parameter  FIFO_DEPTH   = 2  // FIFO DEPTH
 
)(
       input                   rstn,
       input                   srst,
       input                   clk,
       input                   wr_en, // Write
       input [DATA_WIDTH-1:0]  din,
       output                  ready_o,
 
       input                   rd_en, // Read
       output [DATA_WIDTH-1:0] dout,
       output                  valid_o
);
 
 
reg [DATA_WIDTH-1:0]  ram [FIFO_DEPTH-1:0];
reg [ADDR_WIDTH-1:0]  wptr; // write ptr
reg [ADDR_WIDTH-1:0]  rptr; // write ptr
reg [ADDR_WIDTH:0]    status_cnt; // status counter
reg                   empty;
reg                   full;
 
 wire ready_o = ! full;
 wire valid_o = ! empty;
 
 //-----------Code Start---------------------------
 always @ (negedge rstn or posedge clk)
 begin : WRITE_POINTER
   if (rstn==1'b0) begin
     wptr <= 0;
   end else if (srst ) begin
     wptr <= 0;
   end else if (wr_en ) begin
     wptr <= wptr + 1;
   end
 end
 
always @ (negedge rstn or posedge clk)
begin : READ_POINTER
  if (rstn==1'b0) begin
    rptr <= 0;
   end else if (srst ) begin
     rptr <= 0;
  end else if (rd_en) begin
    rptr <= rptr + 1;
  end
end
 
always @ (negedge rstn or posedge clk)
begin : STATUS_COUNTER
  if (rstn==1'b0) begin
       status_cnt <= 0;
  end else if (srst ) begin
       status_cnt <= 0;
  // Read but no write.
  end else if (rd_en &&   (!wr_en) && (status_cnt  != 0)) begin
    status_cnt <= status_cnt - 1;
  // Write but no read.
  end else if (wr_en &&  (!rd_en) && (status_cnt  != FIFO_DEPTH)) begin
    status_cnt <= status_cnt + 1;
  end
end
 
// underflow is not handled
always @ (negedge rstn or posedge clk)
begin : EMPTY_FLAG
  if (rstn==1'b0) begin
       empty <= 1;
  end else if (srst ) begin
       empty <= 1;
  // Read but no write.
  end else if (rd_en &&   (!wr_en) && (status_cnt  == 1)) begin
    empty <= 1;
  // Write
  end else if (wr_en) begin
    empty <= 0;
  end else if (status_cnt  == 0) begin
     empty <= 1;
  end
end
 
// overflow is not handled
always @ (negedge rstn or posedge clk)
begin : FULL_FLAG
  if (rstn==1'b0) begin
       full <= 0;
  end else if (srst ) begin
       full <= 0;
  // Write but no read.
  end else if (wr_en &&  (!rd_en) && (status_cnt  == (FIFO_DEPTH-1))) begin
    full <= 1;
  // Read
  end else if (rd_en &&  (!wr_en) ) begin
    full <= 0;
  end else if (status_cnt  == FIFO_DEPTH) begin
     full <= 1;
  end
end
assign dout = ram[rptr];
 
always @ (posedge clk)
begin
  if (wr_en) ram[wptr] <= din;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	18	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// YiFive cores common library Module ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Sync Fifo with full and empty ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : June 7, 2021 ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45
46			`module spim_fifo #(`
47			`parameter DATA_WIDTH = 32, // Data Width`
48			`parameter ADDR_WIDTH = 1, // Address Width`
49			`parameter FIFO_DEPTH = 2 // FIFO DEPTH`
50
51			`)(`
52			`input rstn,`
53			`input srst,`
54			`input clk,`
55			`input wr_en, // Write`
56			`input [DATA_WIDTH-1:0] din,`
57			`output ready_o,`
58
59			`input rd_en, // Read`
60			`output [DATA_WIDTH-1:0] dout,`
61			`output valid_o`
62			`);`
63
64
65			`reg [DATA_WIDTH-1:0] ram [FIFO_DEPTH-1:0];`
66			`reg [ADDR_WIDTH-1:0] wptr; // write ptr`
67			`reg [ADDR_WIDTH-1:0] rptr; // write ptr`
68			`reg [ADDR_WIDTH:0] status_cnt; // status counter`
69			`reg empty;`
70			`reg full;`
71
72			`wire ready_o = ! full;`
73			`wire valid_o = ! empty;`
74
75			`//-----------Code Start---------------------------`
76			`always @ (negedge rstn or posedge clk)`
77			`begin : WRITE_POINTER`
78			`if (rstn==1'b0) begin`
79			`wptr <= 0;`
80			`end else if (srst ) begin`
81			`wptr <= 0;`
82			`end else if (wr_en ) begin`
83			`wptr <= wptr + 1;`
84			`end`
85			`end`
86
87			`always @ (negedge rstn or posedge clk)`
88			`begin : READ_POINTER`
89			`if (rstn==1'b0) begin`
90			`rptr <= 0;`
91			`end else if (srst ) begin`
92			`rptr <= 0;`
93			`end else if (rd_en) begin`
94			`rptr <= rptr + 1;`
95			`end`
96			`end`
97
98			`always @ (negedge rstn or posedge clk)`
99			`begin : STATUS_COUNTER`
100			`if (rstn==1'b0) begin`
101			`status_cnt <= 0;`
102			`end else if (srst ) begin`
103			`status_cnt <= 0;`
104			`// Read but no write.`
105			`end else if (rd_en && (!wr_en) && (status_cnt != 0)) begin`
106			`status_cnt <= status_cnt - 1;`
107			`// Write but no read.`
108			`end else if (wr_en && (!rd_en) && (status_cnt != FIFO_DEPTH)) begin`
109			`status_cnt <= status_cnt + 1;`
110			`end`
111			`end`
112
113			`// underflow is not handled`
114			`always @ (negedge rstn or posedge clk)`
115			`begin : EMPTY_FLAG`
116			`if (rstn==1'b0) begin`
117			`empty <= 1;`
118			`end else if (srst ) begin`
119			`empty <= 1;`
120			`// Read but no write.`
121			`end else if (rd_en && (!wr_en) && (status_cnt == 1)) begin`
122			`empty <= 1;`
123			`// Write`
124			`end else if (wr_en) begin`
125			`empty <= 0;`
126			`end else if (status_cnt == 0) begin`
127			`empty <= 1;`
128			`end`
129			`end`
130
131			`// overflow is not handled`
132			`always @ (negedge rstn or posedge clk)`
133			`begin : FULL_FLAG`
134			`if (rstn==1'b0) begin`
135			`full <= 0;`
136			`end else if (srst ) begin`
137			`full <= 0;`
138			`// Write but no read.`
139			`end else if (wr_en && (!rd_en) && (status_cnt == (FIFO_DEPTH-1))) begin`
140			`full <= 1;`
141			`// Read`
142			`end else if (rd_en && (!wr_en) ) begin`
143			`full <= 0;`
144			`end else if (status_cnt == FIFO_DEPTH) begin`
145			`full <= 1;`
146			`end`
147			`end`
148			`assign dout = ram[rptr];`
149
150			`always @ (posedge clk)`
151			`begin`
152			`if (wr_en) ram[wptr] <= din;`
153			`end`
154
155
156			`endmodule`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_fifo.sv] - Blame information for rev 18