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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_rx.sv] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SPI RX  Module                                              ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////     SPI RX module                                            ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision :                                                  ////
////     V.0  -  June 8, 2021                                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
module spim_rx #(
                parameter ENDIEAN = 0  // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0
        )
(
    input  logic        clk,
    input  logic        rstn,
    input  logic        en,
    input  logic        rx_edge,
    output logic        rx_done,
    input  logic        sdi0,
    input  logic        sdi1,
    input  logic        sdi2,
    input  logic        sdi3,
    input  logic        en_quad_in,
    input  logic [15:0] counter_in,
    input  logic        counter_in_upd,
    output logic [31:0] data,
    input  logic        data_ready,
    output logic        data_valid,
    output logic        clk_en_o
);
 
  logic [31:0] data_int;
  logic [31:0] data_int_next;
  logic [15:0] counter;
  logic [15:0] counter_trgt;
  logic [15:0] counter_next;
  logic [15:0] counter_trgt_next;
  logic        reg_done;
  enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
 
 
  assign reg_done  = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
 
  // RISV is little endian, so data is converted to little endian format
  assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
  assign rx_done = (counter == (counter_trgt-1)) &  rx_edge;
 
  always_comb
  begin
    if (counter_in_upd)
      counter_trgt_next = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
    else
      counter_trgt_next = counter_trgt;
  end
 
  always_comb
  begin
    rx_NS         = rx_CS;
    clk_en_o      = 1'b0;
    data_int_next = data_int;
    data_valid    = 1'b0;
    counter_next  = counter;
 
    case (rx_CS)
      IDLE: begin
        clk_en_o = 1'b0;
 
        // check first if there is available space instead of later
        if (en) begin
          rx_NS = RECEIVE;
        end
      end
 
      RECEIVE: begin
        clk_en_o = 1'b1;
 
        if (rx_edge) begin
          counter_next = counter + 1;
          if (en_quad_in)
             data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};
          else
             data_int_next = {data_int[30:0],sdi1};
 
          if (rx_done) begin
            counter_next = 0;
            data_valid   = 1'b1;
 
            if (data_ready)
              rx_NS = IDLE;
            else
              rx_NS = WAIT_FIFO_DONE;
          end else if (reg_done) begin
            data_valid = 1'b1;
 
            if (~data_ready) begin
              // no space in the FIFO, wait for free space
              clk_en_o = 1'b0;
              rx_NS    = WAIT_FIFO;
            end
          end
        end
      end
 
      WAIT_FIFO_DONE: begin
        data_valid = 1'b1;
        if (data_ready)
          rx_NS = IDLE;
      end
 
      WAIT_FIFO: begin
        data_valid = 1'b1;
        if (data_ready)
          rx_NS = RECEIVE;
      end
    endcase
  end
 
 
  always_ff @(posedge clk, negedge rstn)
  begin
    if (rstn == 0)
    begin
      counter      <= 0;
      counter_trgt <= 'h8;
      data_int     <= '0;
      rx_CS        <= IDLE;
    end
    else
    begin
      counter      <= counter_next;
      counter_trgt <= counter_trgt_next;
      data_int     <= data_int_next;
      rx_CS        <= rx_NS;
    end
  end
 
endmodule

Line No.	Rev	Author	Line
1	18	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SPI RX Module ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// SPI RX module ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Dinesh Annayya, dinesha@opencores.org ////`
16			`//// ////`
17			`//// Revision : ////`
18			`//// V.0 - June 8, 2021 ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46
47
48			`module spim_rx #(`
49			`parameter ENDIEAN = 0 // 0 - Little, 1 - Big endian, since RISV is Little indian default set 0`
50			`)`
51			`(`
52			`input logic clk,`
53			`input logic rstn,`
54			`input logic en,`
55			`input logic rx_edge,`
56			`output logic rx_done,`
57			`input logic sdi0,`
58			`input logic sdi1,`
59			`input logic sdi2,`
60			`input logic sdi3,`
61			`input logic en_quad_in,`
62			`input logic [15:0] counter_in,`
63			`input logic counter_in_upd,`
64			`output logic [31:0] data,`
65			`input logic data_ready,`
66			`output logic data_valid,`
67			`output logic clk_en_o`
68			`);`
69
70			`logic [31:0] data_int;`
71			`logic [31:0] data_int_next;`
72			`logic [15:0] counter;`
73			`logic [15:0] counter_trgt;`
74			`logic [15:0] counter_next;`
75			`logic [15:0] counter_trgt_next;`
76			`logic reg_done;`
77			`enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;`
78
79
80			`assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) \|\| (en_quad_in && (counter[2:0] == 3'b111));`
81
82			`// RISV is little endian, so data is converted to little endian format`
83			`assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};`
84			`assign rx_done = (counter == (counter_trgt-1)) & rx_edge;`
85
86			`always_comb`
87			`begin`
88			`if (counter_in_upd)`
89			`counter_trgt_next = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;`
90			`else`
91			`counter_trgt_next = counter_trgt;`
92			`end`
93
94			`always_comb`
95			`begin`
96			`rx_NS = rx_CS;`
97			`clk_en_o = 1'b0;`
98			`data_int_next = data_int;`
99			`data_valid = 1'b0;`
100			`counter_next = counter;`
101
102			`case (rx_CS)`
103			`IDLE: begin`
104			`clk_en_o = 1'b0;`
105
106			`// check first if there is available space instead of later`
107			`if (en) begin`
108			`rx_NS = RECEIVE;`
109			`end`
110			`end`
111
112			`RECEIVE: begin`
113			`clk_en_o = 1'b1;`
114
115			`if (rx_edge) begin`
116			`counter_next = counter + 1;`
117			`if (en_quad_in)`
118			`data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};`
119			`else`
120			`data_int_next = {data_int[30:0],sdi1};`
121
122			`if (rx_done) begin`
123			`counter_next = 0;`
124			`data_valid = 1'b1;`
125
126			`if (data_ready)`
127			`rx_NS = IDLE;`
128			`else`
129			`rx_NS = WAIT_FIFO_DONE;`
130			`end else if (reg_done) begin`
131			`data_valid = 1'b1;`
132
133			`if (~data_ready) begin`
134			`// no space in the FIFO, wait for free space`
135			`clk_en_o = 1'b0;`
136			`rx_NS = WAIT_FIFO;`
137			`end`
138			`end`
139			`end`
140			`end`
141
142			`WAIT_FIFO_DONE: begin`
143			`data_valid = 1'b1;`
144			`if (data_ready)`
145			`rx_NS = IDLE;`
146			`end`
147
148			`WAIT_FIFO: begin`
149			`data_valid = 1'b1;`
150			`if (data_ready)`
151			`rx_NS = RECEIVE;`
152			`end`
153			`endcase`
154			`end`
155
156
157			`always_ff @(posedge clk, negedge rstn)`
158			`begin`
159			`if (rstn == 0)`
160			`begin`
161			`counter <= 0;`
162			`counter_trgt <= 'h8;`
163			`data_int <= '0;`
164			`rx_CS <= IDLE;`
165			`end`
166			`else`
167			`begin`
168			`counter <= counter_next;`
169			`counter_trgt <= counter_trgt_next;`
170			`data_int <= data_int_next;`
171			`rx_CS <= rx_NS;`
172			`end`
173			`end`
174
175			`endmodule`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_rx.sv] - Blame information for rev 18