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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_tx.sv] - Blame information for rev 18

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SPI TX  Module                                              ////
////                                                              ////
////  This file is part of the YIFive cores project               ////
////  http://www.opencores.org/cores/yifive/                      ////
////                                                              ////
////  Description                                                 ////
////    This is SPI Master Transmit Word control logic.           ////
////    This logic transmit data upto 32 bit in bit or Quad spi   ////
////    mode                                                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////  Revision:                                                   ////
////       0.1 - 16th Feb 2021, Dinesh A                          ////
////             Initial version                                  ////
////       0.2 - 24th Mar 2021, Dinesh A                          ////
////             1. Comments are added                            ////
////             2. RTL clean-up done and the output are registred////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module spim_tx
(
    // General Input
    input  logic        clk,            // SPI clock
    input  logic        rstn,           // Active low Reset
    input  logic        en,             // Transmit Enable
    input  logic        tx_edge,        // Transmiting Edge
    output logic        tx_done,        // Transmission completion
    output logic        sdo0,           // SPI Dout0
    output logic        sdo1,           // SPI Dout1
    output logic        sdo2,           // SPI Dout2
    output logic        sdo3,           // SPI Dout3
    input  logic        en_quad_in,     // SPI quad mode indication
    input  logic [15:0] counter_in,     // Transmit counter
    input  logic [31:0] txdata,         // 32 bit tranmsit data
    input  logic        data_valid,     // Input data valid
    output logic        data_ready,     // Data in acepted, this for txfifo
    output logic        clk_en_o        // Enable Tx clock
);
 
  logic [31:0]          data_int       ; // Data Input
  logic [31:0]          data_int_next  ; // Next Data Input
  logic [15:0]          counter        ; // Tx Counter
  logic [15:0]          counter_next   ; // tx next counter
  logic [15:0]          counter_trgt   ; // counter exit counter
  logic                 tx32b_done     ;  // 32 bit Transmit done
  logic                 en_quad;
 
  enum logic [0:0] { IDLE, TRANSMIT } tx_CS, tx_NS;
 
  // Counter Exit condition, quad mode div-4 , else actual counter
  always_comb
  begin
     counter_trgt = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
  end
 
  //Indicate end of transmission of all the bytes
  assign tx_done = (counter == counter_trgt) && tx_edge;
 
 
  // Indicate 32 bit data done, usefull for readining next 32b from txfifo
  assign tx32b_done  = (!en_quad && (counter[4:0] == 5'b11111)) || (en_quad && (counter[2:0] == 3'b111)) && tx_edge;
 
 
 
  always_comb
  begin
    tx_NS         = tx_CS;
    clk_en_o      = 1'b0;
    data_int_next = data_int;
    data_ready    = 1'b0;
    counter_next  = counter;
 
    case (tx_CS)
      IDLE: begin
        clk_en_o = 1'b0;
        data_int_next = txdata;
 
        if (en && data_valid) begin
          data_ready    = 1'b1;
          tx_NS         = TRANSMIT;
        end
      end
 
      TRANSMIT: begin
        clk_en_o = 1'b1;
        counter_next = counter + 1;
        data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
 
        if (tx_done) begin
            counter_next = 0;
            // Check if there is next data
            if (en && data_valid) begin
              data_int_next = txdata;
              data_ready    = 1'b1;
              tx_NS         = TRANSMIT;
            end else begin
              clk_en_o = 1'b0;
              tx_NS    = IDLE;
            end
        end else if (tx32b_done) begin
            if (data_valid) begin
              data_int_next = txdata;
              data_ready    = 1'b1;
            end else begin
              clk_en_o = 1'b0;
              tx_NS    = IDLE;
            end
        end
      end
    endcase
  end
 
  always_ff @(posedge clk, negedge rstn)
  begin
    if (~rstn)
    begin
      counter      <= 0;
      data_int     <= 'h0;
      tx_CS        <= IDLE;
      en_quad      <= 0;
    end
    else
    begin
       if(tx_edge) begin
          counter      <= counter_next;
          data_int     <= data_int_next;
          sdo0         <= (en_quad_in) ? data_int_next[28] : data_int_next[31];
          sdo1         <= (en_quad_in) ? data_int_next[29] : 1'b1;
          sdo2         <= (en_quad_in) ? data_int_next[30] : 1'b1;
          sdo3         <= (en_quad_in) ? data_int_next[31] : 1'b1;
          tx_CS        <= tx_NS;
          en_quad      <= en_quad_in;
       end
    end
  end
endmodule

Line No.	Rev	Author	Line
1	18	dinesha	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SPI TX Module ////`
4			`//// ////`
5			`//// This file is part of the YIFive cores project ////`
6			`//// http://www.opencores.org/cores/yifive/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This is SPI Master Transmit Word control logic. ////`
10			`//// This logic transmit data upto 32 bit in bit or Quad spi ////`
11			`//// mode ////`
12			`//// ////`
13			`//// To Do: ////`
14			`//// nothing ////`
15			`//// ////`
16			`//// Author(s): ////`
17			`//// - Dinesh Annayya, dinesha@opencores.org ////`
18			`//// ////`
19			`//// Revision: ////`
20			`//// 0.1 - 16th Feb 2021, Dinesh A ////`
21			`//// Initial version ////`
22			`//// 0.2 - 24th Mar 2021, Dinesh A ////`
23			`//// 1. Comments are added ////`
24			`//// 2. RTL clean-up done and the output are registred////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27			`//// ////`
28			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
29			`//// ////`
30			`//// This source file may be used and distributed without ////`
31			`//// restriction provided that this copyright statement is not ////`
32			`//// removed from the file and that any derivative work contains ////`
33			`//// the original copyright notice and the associated disclaimer. ////`
34			`//// ////`
35			`//// This source file is free software; you can redistribute it ////`
36			`//// and/or modify it under the terms of the GNU Lesser General ////`
37			`//// Public License as published by the Free Software Foundation; ////`
38			`//// either version 2.1 of the License, or (at your option) any ////`
39			`//// later version. ////`
40			`//// ////`
41			`//// This source is distributed in the hope that it will be ////`
42			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
43			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
44			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
45			`//// details. ////`
46			`//// ////`
47			`//// You should have received a copy of the GNU Lesser General ////`
48			`//// Public License along with this source; if not, download it ////`
49			`//// from http://www.opencores.org/lgpl.shtml ////`
50			`//// ////`
51			`//////////////////////////////////////////////////////////////////////`
52
53			`module spim_tx`
54			`(`
55			`// General Input`
56			`input logic clk, // SPI clock`
57			`input logic rstn, // Active low Reset`
58			`input logic en, // Transmit Enable`
59			`input logic tx_edge, // Transmiting Edge`
60			`output logic tx_done, // Transmission completion`
61			`output logic sdo0, // SPI Dout0`
62			`output logic sdo1, // SPI Dout1`
63			`output logic sdo2, // SPI Dout2`
64			`output logic sdo3, // SPI Dout3`
65			`input logic en_quad_in, // SPI quad mode indication`
66			`input logic [15:0] counter_in, // Transmit counter`
67			`input logic [31:0] txdata, // 32 bit tranmsit data`
68			`input logic data_valid, // Input data valid`
69			`output logic data_ready, // Data in acepted, this for txfifo`
70			`output logic clk_en_o // Enable Tx clock`
71			`);`
72
73			`logic [31:0] data_int ; // Data Input`
74			`logic [31:0] data_int_next ; // Next Data Input`
75			`logic [15:0] counter ; // Tx Counter`
76			`logic [15:0] counter_next ; // tx next counter`
77			`logic [15:0] counter_trgt ; // counter exit counter`
78			`logic tx32b_done ; // 32 bit Transmit done`
79			`logic en_quad;`
80
81			`enum logic [0:0] { IDLE, TRANSMIT } tx_CS, tx_NS;`
82
83			`// Counter Exit condition, quad mode div-4 , else actual counter`
84			`always_comb`
85			`begin`
86			`counter_trgt = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;`
87			`end`
88
89			`//Indicate end of transmission of all the bytes`
90			`assign tx_done = (counter == counter_trgt) && tx_edge;`
91
92
93			`// Indicate 32 bit data done, usefull for readining next 32b from txfifo`
94			`assign tx32b_done = (!en_quad && (counter[4:0] == 5'b11111)) \|\| (en_quad && (counter[2:0] == 3'b111)) && tx_edge;`
95
96
97
98			`always_comb`
99			`begin`
100			`tx_NS = tx_CS;`
101			`clk_en_o = 1'b0;`
102			`data_int_next = data_int;`
103			`data_ready = 1'b0;`
104			`counter_next = counter;`
105
106			`case (tx_CS)`
107			`IDLE: begin`
108			`clk_en_o = 1'b0;`
109			`data_int_next = txdata;`
110
111			`if (en && data_valid) begin`
112			`data_ready = 1'b1;`
113			`tx_NS = TRANSMIT;`
114			`end`
115			`end`
116
117			`TRANSMIT: begin`
118			`clk_en_o = 1'b1;`
119			`counter_next = counter + 1;`
120			`data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};`
121
122			`if (tx_done) begin`
123			`counter_next = 0;`
124			`// Check if there is next data`
125			`if (en && data_valid) begin`
126			`data_int_next = txdata;`
127			`data_ready = 1'b1;`
128			`tx_NS = TRANSMIT;`
129			`end else begin`
130			`clk_en_o = 1'b0;`
131			`tx_NS = IDLE;`
132			`end`
133			`end else if (tx32b_done) begin`
134			`if (data_valid) begin`
135			`data_int_next = txdata;`
136			`data_ready = 1'b1;`
137			`end else begin`
138			`clk_en_o = 1'b0;`
139			`tx_NS = IDLE;`
140			`end`
141			`end`
142			`end`
143			`endcase`
144			`end`
145
146			`always_ff @(posedge clk, negedge rstn)`
147			`begin`
148			`if (~rstn)`
149			`begin`
150			`counter <= 0;`
151			`data_int <= 'h0;`
152			`tx_CS <= IDLE;`
153			`en_quad <= 0;`
154			`end`
155			`else`
156			`begin`
157			`if(tx_edge) begin`
158			`counter <= counter_next;`
159			`data_int <= data_int_next;`
160			`sdo0 <= (en_quad_in) ? data_int_next[28] : data_int_next[31];`
161			`sdo1 <= (en_quad_in) ? data_int_next[29] : 1'b1;`
162			`sdo2 <= (en_quad_in) ? data_int_next[30] : 1'b1;`
163			`sdo3 <= (en_quad_in) ? data_int_next[31] : 1'b1;`
164			`tx_CS <= tx_NS;`
165			`en_quad <= en_quad_in;`
166			`end`
167			`end`
168			`end`
169			`endmodule`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [spi_master/] [src/] [spim_tx.sv] - Blame information for rev 18