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dinesha |
#------------------------------------------------------------------------------
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# Makefile for SCR1
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#------------------------------------------------------------------------------
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# PARAMETERS
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# CFG =
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# BUS =
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export CFG ?= MAX
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export BUS ?= AHB
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ifeq ($(CFG), MAX)
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# Predefined configuration SCR1_CFG_RV32IMC_MAX
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override ARCH := IMC
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override VECT_IRQ := 1
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override IPIC := 1
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override TCM := 1
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override SIM_CFG_DEF := SCR1_CFG_RV32IMC_MAX
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else
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ifeq ($(CFG), BASE)
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# Predefined configuration SCR1_CFG_RV32IC_BASE
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override ARCH := IC
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override VECT_IRQ := 1
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override IPIC := 1
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override TCM := 1
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override SIM_CFG_DEF := SCR1_CFG_RV32IC_BASE
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else
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ifeq ($(CFG), MIN)
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# Predefined configuration SCR1_CFG_RV32EC_MIN
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override ARCH := EC
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override VECT_IRQ := 0
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override IPIC := 0
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override TCM := 1
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override SIM_CFG_DEF := SCR1_CFG_RV32EC_MIN
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else
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# CUSTOM configuration. Parameters can be overwritten
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# These options are for compiling tests only. Set the corresponding RTL parameters manually in the file scr1_arch_description.svh.
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# ARCH =
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# VECT_IRQ = <0, 1>
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# IPIC = <0, 1>
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# TCM = <0, 1>
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ARCH ?= IMC
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VECT_IRQ ?= 0
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IPIC ?= 0
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TCM ?= 0
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SIM_CFG_DEF = SCR1_CFG_$(CFG)
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endif
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endif
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endif
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# export all overrided variables
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export ARCH
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export VECT_IRQ
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export IPIC
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export TCM
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export SIM_CFG_DEF
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ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z)
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BUS_lowercase = $(shell echo $(BUS) | tr A-Z a-z)
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ifeq ($(ARCH_lowercase),)
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ARCH_tmp = imc
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else
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ifneq (,$(findstring e,$(ARCH_lowercase)))
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ARCH_tmp += e
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EXT_CFLAGS += -D__RVE_EXT
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else
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ARCH_tmp += i
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endif
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ifneq (,$(findstring m,$(ARCH_lowercase)))
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ARCH_tmp := $(ARCH_tmp)m
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endif
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ifneq (,$(findstring c,$(ARCH_lowercase)))
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ARCH_tmp := $(ARCH_tmp)c
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EXT_CFLAGS += -D__RVC_EXT
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endif
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endif
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override ARCH=$(ARCH_tmp)
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# Use this parameter to enable tracelog
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TRACE ?= 0
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ifeq ($(TRACE), 1)
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export SIM_TRACE_DEF = SCR1_TRACE_LOG_EN
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else
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export SIM_TRACE_DEF = SCR1_TRACE_LOG_DIS
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endif
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# Use this parameter to pass additional options for simulation build command
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SIM_BUILD_OPTS ?=
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# Use this parameter to set the list of tests to run
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# TARGETS =
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export TARGETS :=
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export ABI ?= ilp32
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# Testbench memory delay patterns\
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(FFFFFFFF - no delay, 00000000 - random delay, 00000001 - max delay)
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imem_pattern ?= FFFFFFFF
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dmem_pattern ?= FFFFFFFF
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VCS_OPTS ?=
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MODELSIM_OPTS ?=
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NCSIM_OPTS ?=
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VERILATOR_OPTS ?=
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current_goal := $(MAKECMDGOALS:run_%=%)
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ifeq ($(current_goal),)
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current_goal := verilator
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endif
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# Paths
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export root_dir := $(shell pwd)
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export tst_dir := $(root_dir)/sim/tests
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export inc_dir := $(tst_dir)/common
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export bld_dir := $(root_dir)/build/$(current_goal)_$(BUS)_$(CFG)_$(ARCH)_IPIC_$(IPIC)_TCM_$(TCM)_VIRQ_$(VECT_IRQ)_TRACE_$(TRACE)
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test_results := $(bld_dir)/test_results.txt
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test_info := $(bld_dir)/test_info
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sim_results := $(bld_dir)/sim_results.txt
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todo_list := $(bld_dir)/todo.txt
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# Environment
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export CROSS_PREFIX ?= riscv64-unknown-elf-
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export RISCV_GCC ?= $(CROSS_PREFIX)gcc
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export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
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export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
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export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s
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#--
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ifneq (,$(findstring axi,$(BUS_lowercase)))
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export rtl_top_files := axi_top.files
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export rtl_tb_files := axi_tb.files
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export top_module := scr1_top_tb_axi
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else
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export rtl_top_files := ahb_top.files
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export rtl_tb_files := ahb_tb.files
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export top_module := scr1_top_tb_ahb
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endif
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ifneq (,$(findstring e,$(ARCH_lowercase)))
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# Tests can be compiled for RVE only if gcc version 8.0.0 or higher
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GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
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ifeq "$(GCCVERSIONGT7)" "1"
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ABI := ilp32e
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endif
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endif
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#--
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ifeq (,$(findstring e,$(ARCH_lowercase)))
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# These tests cannot be compiled for RVE
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# Comment this target if you don't want to run the riscv_isa
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TARGETS += riscv_isa
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# Comment this target if you don't want to run the riscv_compliance
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TARGETS += riscv_compliance
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endif
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# Comment this target if you don't want to run the isr_sample
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TARGETS += isr_sample
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# Comment this target if you don't want to run the coremark
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TARGETS += coremark
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# Comment this target if you don't want to run the dhrystone
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TARGETS += dhrystone21
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# Comment this target if you don't want to run the hello test
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TARGETS += hello
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# Targets
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.PHONY: tests run_modelsim run_vcs run_ncsim run_verilator run_verilator_wf
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default: clean_test_list run_verilator
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clean_test_list:
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rm -f $(test_info)
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echo_out: tests
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@echo " Test | build | simulation " ;
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@echo "$$(cat $(test_results))"
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tests: $(TARGETS)
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$(test_info): clean_hex tests
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cd $(bld_dir)
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isr_sample: | $(bld_dir)
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$(MAKE) -C $(tst_dir)/isr_sample ARCH=$(ARCH) IPIC=$(IPIC) VECT_IRQ=$(VECT_IRQ)
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dhrystone21: | $(bld_dir)
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$(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
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coremark: | $(bld_dir)
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-$(MAKE) -C $(tst_dir)/benchmarks/coremark EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
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riscv_isa: | $(bld_dir)
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$(MAKE) -C $(tst_dir)/riscv_isa ARCH=$(ARCH)
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riscv_compliance: | $(bld_dir)
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$(MAKE) -C $(tst_dir)/riscv_compliance ARCH=$(ARCH)
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hello: | $(bld_dir)
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-$(MAKE) -C $(tst_dir)/hello EXT_CFLAGS="$(EXT_CFLAGS)" ARCH=$(ARCH)
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clean_hex: | $(bld_dir)
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$(RM) $(bld_dir)/*.hex
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$(bld_dir):
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mkdir -p $(bld_dir)
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run_vcs: $(test_info)
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$(MAKE) -C $(root_dir)/sim build_vcs SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
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printf "" > $(test_results);
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cd $(bld_dir); \
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$(bld_dir)/simv -V \
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+test_info=$(test_info) \
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+test_results=$(test_results) \
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+imem_pattern=$(imem_pattern) \
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+dmem_pattern=$(dmem_pattern) \
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$(VCS_OPTS) | tee $(sim_results) ;\
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printf " Test | build | simulation \n" ; \
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printf "$$(cat $(test_results)) \n"
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run_modelsim: $(test_info)
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$(MAKE) -C $(root_dir)/sim build_modelsim SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS); \
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printf "" > $(test_results); \
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cd $(bld_dir); \
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vsim -c -do "run -all" +nowarn3691 \
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+test_info=$(test_info) \
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+test_results=$(test_results) \
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+imem_pattern=$(imem_pattern) \
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+dmem_pattern=$(dmem_pattern) \
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work.$(top_module) \
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$(MODELSIM_OPTS) | tee $(sim_results) ;\
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printf "Simulation performed on $$(vsim -version) \n" ;\
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printf " Test | build | simulation \n" ; \
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printf "$$(cat $(test_results)) \n"
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run_ncsim: $(test_info)
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$(MAKE) -C $(root_dir)/sim build_ncsim SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
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printf "" > $(test_results);
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cd $(bld_dir); \
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irun \
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-R \
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-64bit \
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+test_info=$(test_info) \
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+test_results=$(test_results) \
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+imem_pattern=$(imem_pattern) \
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+dmem_pattern=$(dmem_pattern) \
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$(NCSIM_OPTS) | tee $(sim_results) ;\
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printf "Simulation performed on $$(irun -version) \n" ;\
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printf " Test | build | simulation \n" ; \
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printf "$$(cat $(test_results)) \n"
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run_verilator: $(test_info)
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$(MAKE) -C $(root_dir)/sim build_verilator SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
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printf "" > $(test_results);
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cd $(bld_dir); \
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echo $(top_module) | tee $(sim_results); \
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$(bld_dir)/verilator/V$(top_module) \
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+test_info=$(test_info) \
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+test_results=$(test_results) \
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+imem_pattern=$(imem_pattern) \
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+dmem_pattern=$(dmem_pattern) \
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$(VERILATOR_OPTS) | tee -a $(sim_results) ;\
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printf "Simulation performed on $$(verilator -version) \n" ;\
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printf " Test | build | simulation \n" ; \
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printf "$$(cat $(test_results)) \n"
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run_verilator_wf: $(test_info)
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$(MAKE) -C $(root_dir)/sim build_verilator_wf SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS);
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printf "" > $(test_results);
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| 277 |
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cd $(bld_dir); \
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echo $(top_module) | tee $(sim_results); \
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| 279 |
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$(bld_dir)/verilator/V$(top_module) \
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+test_info=$(test_info) \
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+test_results=$(test_results) \
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| 282 |
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+imem_pattern=$(imem_pattern) \
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| 283 |
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+dmem_pattern=$(dmem_pattern) \
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| 284 |
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$(VERILATOR_OPTS) | tee -a $(sim_results) ;\
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| 285 |
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printf "Simulation performed on $$(verilator -version) \n" ;\
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| 286 |
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printf " Test | build | simulation \n" ; \
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| 287 |
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printf "$$(cat $(test_results)) \n"
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| 288 |
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clean:
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| 289 |
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$(MAKE) -C $(tst_dir)/benchmarks/dhrystone21 clean
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| 290 |
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$(MAKE) -C $(tst_dir)/riscv_isa clean
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| 291 |
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$(MAKE) -C $(tst_dir)/riscv_compliance clean
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| 292 |
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$(RM) -R $(root_dir)/build/*
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| 293 |
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$(RM) $(test_info)
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