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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [crt.S] - Blame information for rev 22

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/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
/// @file       
///
 
#include "riscv_csr_encoding.h"
#include "sc_test.h"
 
# define LREG lw
# define SREG sw
# define REGBYTES 4
 
    .globl _start
    .globl main
    .globl trap_entry
    .globl handle_trap
    .globl sc_exit
    .weak trap_entry, handle_trap
 
    .text
    .org (64*3)
    .balign 64
machine_trap_entry:
    j trap_entry
 
    .balign 64
 
_start:
#ifndef __RVE_EXT
    zero_int_regs 1, 31
#else
    zero_int_regs 1, 15
#endif
    # Global pointer init
    .option push
    .option norelax
    la    gp, __global_pointer$
    .option pop
    # clear bss
    la      a1, __BSS_START__
    la      a2, __BSS_END__
    j       4f
3:  sw      zero, 0(a1)
    add     a1, a1, 4
4:  bne     a1, a2, 3b
    la      sp, __C_STACK_TOP__
 
    // Timer init
    li      t0, mtime_ctrl
    li      t1, (1 << SCR1_MTIME_CTRL_EN)   // enable, use internal clock
    sw      t1, (t0)
    li      t0, mtime_div
    li      t1, (100-1)                     // divide by 100
    sw      t1, (t0)
    li      t0, mtimecmp
    li      t1, -1
    sw      t1, (t0)                        // max value for mtimecmp
    sw      t1, 4(t0)
 
    li      a0, 0
    li      a1, 0
    jal     main
    j       sc_exit
 
trap_entry:
    addi sp, sp, -272
 
    SREG x1, 1*REGBYTES(sp)
    SREG x2, 2*REGBYTES(sp)
    SREG x3, 3*REGBYTES(sp)
    SREG x4, 4*REGBYTES(sp)
    SREG x5, 5*REGBYTES(sp)
    SREG x6, 6*REGBYTES(sp)
    SREG x7, 7*REGBYTES(sp)
    SREG x8, 8*REGBYTES(sp)
    SREG x9, 9*REGBYTES(sp)
    SREG x10, 10*REGBYTES(sp)
    SREG x11, 11*REGBYTES(sp)
    SREG x12, 12*REGBYTES(sp)
    SREG x13, 13*REGBYTES(sp)
    SREG x14, 14*REGBYTES(sp)
    SREG x15, 15*REGBYTES(sp)
#ifndef __RVE_EXT
    SREG x16, 16*REGBYTES(sp)
    SREG x17, 17*REGBYTES(sp)
    SREG x18, 18*REGBYTES(sp)
    SREG x19, 19*REGBYTES(sp)
    SREG x20, 20*REGBYTES(sp)
    SREG x21, 21*REGBYTES(sp)
    SREG x22, 22*REGBYTES(sp)
    SREG x23, 23*REGBYTES(sp)
    SREG x24, 24*REGBYTES(sp)
    SREG x25, 25*REGBYTES(sp)
    SREG x26, 26*REGBYTES(sp)
    SREG x27, 27*REGBYTES(sp)
    SREG x28, 28*REGBYTES(sp)
    SREG x29, 29*REGBYTES(sp)
    SREG x30, 30*REGBYTES(sp)
    SREG x31, 31*REGBYTES(sp)
#endif // __RVE_EXT
 
    csrr a0, mcause
    csrr a1, mepc
    mv a2, sp
    jal handle_trap
 
    LREG x1, 1*REGBYTES(sp)
    LREG x2, 2*REGBYTES(sp)
    LREG x3, 3*REGBYTES(sp)
    LREG x4, 4*REGBYTES(sp)
    LREG x5, 5*REGBYTES(sp)
    LREG x6, 6*REGBYTES(sp)
    LREG x7, 7*REGBYTES(sp)
    LREG x8, 8*REGBYTES(sp)
    LREG x9, 9*REGBYTES(sp)
    LREG x10, 10*REGBYTES(sp)
    LREG x11, 11*REGBYTES(sp)
    LREG x12, 12*REGBYTES(sp)
    LREG x13, 13*REGBYTES(sp)
    LREG x14, 14*REGBYTES(sp)
    LREG x15, 15*REGBYTES(sp)
#ifndef __RVE_EXT
    LREG x16, 16*REGBYTES(sp)
    LREG x17, 17*REGBYTES(sp)
    LREG x18, 18*REGBYTES(sp)
    LREG x19, 19*REGBYTES(sp)
    LREG x20, 20*REGBYTES(sp)
    LREG x21, 21*REGBYTES(sp)
    LREG x22, 22*REGBYTES(sp)
    LREG x23, 23*REGBYTES(sp)
    LREG x24, 24*REGBYTES(sp)
    LREG x25, 25*REGBYTES(sp)
    LREG x26, 26*REGBYTES(sp)
    LREG x27, 27*REGBYTES(sp)
    LREG x28, 28*REGBYTES(sp)
    LREG x29, 29*REGBYTES(sp)
    LREG x30, 30*REGBYTES(sp)
    LREG x31, 31*REGBYTES(sp)
#endif // __RVE_EXT
 
    addi sp, sp, 272
    mret
 
handle_trap:
    j SIM_EXIT
 
// end of crt.S

Line No.	Rev	Author	Line
1	22	dinesha	`/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details`
2			`/// @file`
3			`///`
4
5			`#include "riscv_csr_encoding.h"`
6			`#include "sc_test.h"`
7
8			`# define LREG lw`
9			`# define SREG sw`
10			`# define REGBYTES 4`
11
12			`.globl _start`
13			`.globl main`
14			`.globl trap_entry`
15			`.globl handle_trap`
16			`.globl sc_exit`
17			`.weak trap_entry, handle_trap`
18
19			`.text`
20			`.org (64*3)`
21			`.balign 64`
22			`machine_trap_entry:`
23			`j trap_entry`
24
25			`.balign 64`
26
27			`_start:`
28			`#ifndef __RVE_EXT`
29			`zero_int_regs 1, 31`
30			`#else`
31			`zero_int_regs 1, 15`
32			`#endif`
33			`# Global pointer init`
34			`.option push`
35			`.option norelax`
36			`la gp, __global_pointer$`
37			`.option pop`
38			`# clear bss`
39			`la a1, __BSS_START__`
40			`la a2, __BSS_END__`
41			`j 4f`
42			`3: sw zero, 0(a1)`
43			`add a1, a1, 4`
44			`4: bne a1, a2, 3b`
45			`la sp, __C_STACK_TOP__`
46
47			`// Timer init`
48			`li t0, mtime_ctrl`
49			`li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock`
50			`sw t1, (t0)`
51			`li t0, mtime_div`
52			`li t1, (100-1) // divide by 100`
53			`sw t1, (t0)`
54			`li t0, mtimecmp`
55			`li t1, -1`
56			`sw t1, (t0) // max value for mtimecmp`
57			`sw t1, 4(t0)`
58
59			`li a0, 0`
60			`li a1, 0`
61			`jal main`
62			`j sc_exit`
63
64			`trap_entry:`
65			`addi sp, sp, -272`
66
67			`SREG x1, 1*REGBYTES(sp)`
68			`SREG x2, 2*REGBYTES(sp)`
69			`SREG x3, 3*REGBYTES(sp)`
70			`SREG x4, 4*REGBYTES(sp)`
71			`SREG x5, 5*REGBYTES(sp)`
72			`SREG x6, 6*REGBYTES(sp)`
73			`SREG x7, 7*REGBYTES(sp)`
74			`SREG x8, 8*REGBYTES(sp)`
75			`SREG x9, 9*REGBYTES(sp)`
76			`SREG x10, 10*REGBYTES(sp)`
77			`SREG x11, 11*REGBYTES(sp)`
78			`SREG x12, 12*REGBYTES(sp)`
79			`SREG x13, 13*REGBYTES(sp)`
80			`SREG x14, 14*REGBYTES(sp)`
81			`SREG x15, 15*REGBYTES(sp)`
82			`#ifndef __RVE_EXT`
83			`SREG x16, 16*REGBYTES(sp)`
84			`SREG x17, 17*REGBYTES(sp)`
85			`SREG x18, 18*REGBYTES(sp)`
86			`SREG x19, 19*REGBYTES(sp)`
87			`SREG x20, 20*REGBYTES(sp)`
88			`SREG x21, 21*REGBYTES(sp)`
89			`SREG x22, 22*REGBYTES(sp)`
90			`SREG x23, 23*REGBYTES(sp)`
91			`SREG x24, 24*REGBYTES(sp)`
92			`SREG x25, 25*REGBYTES(sp)`
93			`SREG x26, 26*REGBYTES(sp)`
94			`SREG x27, 27*REGBYTES(sp)`
95			`SREG x28, 28*REGBYTES(sp)`
96			`SREG x29, 29*REGBYTES(sp)`
97			`SREG x30, 30*REGBYTES(sp)`
98			`SREG x31, 31*REGBYTES(sp)`
99			`#endif // __RVE_EXT`
100
101			`csrr a0, mcause`
102			`csrr a1, mepc`
103			`mv a2, sp`
104			`jal handle_trap`
105
106			`LREG x1, 1*REGBYTES(sp)`
107			`LREG x2, 2*REGBYTES(sp)`
108			`LREG x3, 3*REGBYTES(sp)`
109			`LREG x4, 4*REGBYTES(sp)`
110			`LREG x5, 5*REGBYTES(sp)`
111			`LREG x6, 6*REGBYTES(sp)`
112			`LREG x7, 7*REGBYTES(sp)`
113			`LREG x8, 8*REGBYTES(sp)`
114			`LREG x9, 9*REGBYTES(sp)`
115			`LREG x10, 10*REGBYTES(sp)`
116			`LREG x11, 11*REGBYTES(sp)`
117			`LREG x12, 12*REGBYTES(sp)`
118			`LREG x13, 13*REGBYTES(sp)`
119			`LREG x14, 14*REGBYTES(sp)`
120			`LREG x15, 15*REGBYTES(sp)`
121			`#ifndef __RVE_EXT`
122			`LREG x16, 16*REGBYTES(sp)`
123			`LREG x17, 17*REGBYTES(sp)`
124			`LREG x18, 18*REGBYTES(sp)`
125			`LREG x19, 19*REGBYTES(sp)`
126			`LREG x20, 20*REGBYTES(sp)`
127			`LREG x21, 21*REGBYTES(sp)`
128			`LREG x22, 22*REGBYTES(sp)`
129			`LREG x23, 23*REGBYTES(sp)`
130			`LREG x24, 24*REGBYTES(sp)`
131			`LREG x25, 25*REGBYTES(sp)`
132			`LREG x26, 26*REGBYTES(sp)`
133			`LREG x27, 27*REGBYTES(sp)`
134			`LREG x28, 28*REGBYTES(sp)`
135			`LREG x29, 29*REGBYTES(sp)`
136			`LREG x30, 30*REGBYTES(sp)`
137			`LREG x31, 31*REGBYTES(sp)`
138			`#endif // __RVE_EXT`
139
140			`addi sp, sp, 272`
141			`mret`
142
143			`handle_trap:`
144			`j SIM_EXIT`
145
146			`// end of crt.S`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [crt.S] - Blame information for rev 22