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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [crt_tcm.S] - Blame information for rev 22

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/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
/// @file       
///
 
#include "riscv_csr_encoding.h"
#include "reloc.h"
#include "sc_test.h"
 
# define LREG lw
# define SREG sw
# define REGBYTES 4
 
    .globl _start
    .globl main
    .globl trap_entry
    .globl handle_trap
    .globl sc_exit
    .weak trap_entry, handle_trap
 
    .section .text.init
    .org (64*3)
    .align 6;
machine_trap_entry:
    j trap_entry
 
    .align 6
_start:
#ifndef __RVE_EXT
    zero_int_regs 1, 31
#else
    zero_int_regs 1, 15
#endif
    # Global pointer init
    .option push
    .option norelax
    la    gp, __global_pointer$
    .option pop
 
    RELOC_PROC;
 
    // init tdata
    mv    a1, tp
    la    a2, _tdata_end
    j     6f
5:  lw    a3, 0(a0)
    sw    a3, 0(a1)
    add   a0, a0, 4
    add   a1, a1, 4
6:  bne   a0, a2, 5b
    // clear tbss
    j     8f
7:  sw    zero, 0(a1)
    add   a1, a1, 4
8:  bne   a1, a4, 7b
 
    // Timer init
    li    t0, mtime_ctrl
    li    t1, (1 << SCR1_MTIME_CTRL_EN)   // enable, use internal clock
    sw    t1, (t0)
    li    t0, mtime_div
    li    t1, (100-1)                     // divide by 100
    sw    t1, (t0)
    li    t0, mtimecmp
    li    t1, -1
    sw    t1, (t0)                        // max value for mtimecmp
    sw    t1, 4(t0)
 
    li    a0, 0
    li    a1, 0
9:  auipc t0, %pcrel_hi(main)
    jalr  t0, %pcrel_lo(9b)
    la    t0, sc_exit
    //j     sc_exit
 
trap_entry:
    addi sp, sp, -272
 
    SREG x1, 1*REGBYTES(sp)
    SREG x2, 2*REGBYTES(sp)
    SREG x3, 3*REGBYTES(sp)
    SREG x4, 4*REGBYTES(sp)
    SREG x5, 5*REGBYTES(sp)
    SREG x6, 6*REGBYTES(sp)
    SREG x7, 7*REGBYTES(sp)
    SREG x8, 8*REGBYTES(sp)
    SREG x9, 9*REGBYTES(sp)
    SREG x10, 10*REGBYTES(sp)
    SREG x11, 11*REGBYTES(sp)
    SREG x12, 12*REGBYTES(sp)
    SREG x13, 13*REGBYTES(sp)
    SREG x14, 14*REGBYTES(sp)
    SREG x15, 15*REGBYTES(sp)
#ifndef __RVE_EXT
    SREG x16, 16*REGBYTES(sp)
    SREG x17, 17*REGBYTES(sp)
    SREG x18, 18*REGBYTES(sp)
    SREG x19, 19*REGBYTES(sp)
    SREG x20, 20*REGBYTES(sp)
    SREG x21, 21*REGBYTES(sp)
    SREG x22, 22*REGBYTES(sp)
    SREG x23, 23*REGBYTES(sp)
    SREG x24, 24*REGBYTES(sp)
    SREG x25, 25*REGBYTES(sp)
    SREG x26, 26*REGBYTES(sp)
    SREG x27, 27*REGBYTES(sp)
    SREG x28, 28*REGBYTES(sp)
    SREG x29, 29*REGBYTES(sp)
    SREG x30, 30*REGBYTES(sp)
    SREG x31, 31*REGBYTES(sp)
#endif // __RVE_EXT
 
    csrr a0, mcause
    csrr a1, mepc
    mv a2, sp
    jal handle_trap
 
    LREG x1, 1*REGBYTES(sp)
    LREG x2, 2*REGBYTES(sp)
    LREG x3, 3*REGBYTES(sp)
    LREG x4, 4*REGBYTES(sp)
    LREG x5, 5*REGBYTES(sp)
    LREG x6, 6*REGBYTES(sp)
    LREG x7, 7*REGBYTES(sp)
    LREG x8, 8*REGBYTES(sp)
    LREG x9, 9*REGBYTES(sp)
    LREG x10, 10*REGBYTES(sp)
    LREG x11, 11*REGBYTES(sp)
    LREG x12, 12*REGBYTES(sp)
    LREG x13, 13*REGBYTES(sp)
    LREG x14, 14*REGBYTES(sp)
    LREG x15, 15*REGBYTES(sp)
#ifndef __RVE_EXT
    LREG x16, 16*REGBYTES(sp)
    LREG x17, 17*REGBYTES(sp)
    LREG x18, 18*REGBYTES(sp)
    LREG x19, 19*REGBYTES(sp)
    LREG x20, 20*REGBYTES(sp)
    LREG x21, 21*REGBYTES(sp)
    LREG x22, 22*REGBYTES(sp)
    LREG x23, 23*REGBYTES(sp)
    LREG x24, 24*REGBYTES(sp)
    LREG x25, 25*REGBYTES(sp)
    LREG x26, 26*REGBYTES(sp)
    LREG x27, 27*REGBYTES(sp)
    LREG x28, 28*REGBYTES(sp)
    LREG x29, 29*REGBYTES(sp)
    LREG x30, 30*REGBYTES(sp)
    LREG x31, 31*REGBYTES(sp)
#endif // __RVE_EXT
 
    addi sp, sp, 272
    mret
 
handle_trap:
    j SIM_EXIT
 
// end of crt.S

Line No.	Rev	Author	Line
1	22	dinesha	`/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details`
2			`/// @file`
3			`///`
4
5			`#include "riscv_csr_encoding.h"`
6			`#include "reloc.h"`
7			`#include "sc_test.h"`
8
9			`# define LREG lw`
10			`# define SREG sw`
11			`# define REGBYTES 4`
12
13			`.globl _start`
14			`.globl main`
15			`.globl trap_entry`
16			`.globl handle_trap`
17			`.globl sc_exit`
18			`.weak trap_entry, handle_trap`
19
20			`.section .text.init`
21			`.org (64*3)`
22			`.align 6;`
23			`machine_trap_entry:`
24			`j trap_entry`
25
26			`.align 6`
27			`_start:`
28			`#ifndef __RVE_EXT`
29			`zero_int_regs 1, 31`
30			`#else`
31			`zero_int_regs 1, 15`
32			`#endif`
33			`# Global pointer init`
34			`.option push`
35			`.option norelax`
36			`la gp, __global_pointer$`
37			`.option pop`
38
39			`RELOC_PROC;`
40
41			`// init tdata`
42			`mv a1, tp`
43			`la a2, _tdata_end`
44			`j 6f`
45			`5: lw a3, 0(a0)`
46			`sw a3, 0(a1)`
47			`add a0, a0, 4`
48			`add a1, a1, 4`
49			`6: bne a0, a2, 5b`
50			`// clear tbss`
51			`j 8f`
52			`7: sw zero, 0(a1)`
53			`add a1, a1, 4`
54			`8: bne a1, a4, 7b`
55
56			`// Timer init`
57			`li t0, mtime_ctrl`
58			`li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock`
59			`sw t1, (t0)`
60			`li t0, mtime_div`
61			`li t1, (100-1) // divide by 100`
62			`sw t1, (t0)`
63			`li t0, mtimecmp`
64			`li t1, -1`
65			`sw t1, (t0) // max value for mtimecmp`
66			`sw t1, 4(t0)`
67
68			`li a0, 0`
69			`li a1, 0`
70			`9: auipc t0, %pcrel_hi(main)`
71			`jalr t0, %pcrel_lo(9b)`
72			`la t0, sc_exit`
73			`//j sc_exit`
74
75			`trap_entry:`
76			`addi sp, sp, -272`
77
78			`SREG x1, 1*REGBYTES(sp)`
79			`SREG x2, 2*REGBYTES(sp)`
80			`SREG x3, 3*REGBYTES(sp)`
81			`SREG x4, 4*REGBYTES(sp)`
82			`SREG x5, 5*REGBYTES(sp)`
83			`SREG x6, 6*REGBYTES(sp)`
84			`SREG x7, 7*REGBYTES(sp)`
85			`SREG x8, 8*REGBYTES(sp)`
86			`SREG x9, 9*REGBYTES(sp)`
87			`SREG x10, 10*REGBYTES(sp)`
88			`SREG x11, 11*REGBYTES(sp)`
89			`SREG x12, 12*REGBYTES(sp)`
90			`SREG x13, 13*REGBYTES(sp)`
91			`SREG x14, 14*REGBYTES(sp)`
92			`SREG x15, 15*REGBYTES(sp)`
93			`#ifndef __RVE_EXT`
94			`SREG x16, 16*REGBYTES(sp)`
95			`SREG x17, 17*REGBYTES(sp)`
96			`SREG x18, 18*REGBYTES(sp)`
97			`SREG x19, 19*REGBYTES(sp)`
98			`SREG x20, 20*REGBYTES(sp)`
99			`SREG x21, 21*REGBYTES(sp)`
100			`SREG x22, 22*REGBYTES(sp)`
101			`SREG x23, 23*REGBYTES(sp)`
102			`SREG x24, 24*REGBYTES(sp)`
103			`SREG x25, 25*REGBYTES(sp)`
104			`SREG x26, 26*REGBYTES(sp)`
105			`SREG x27, 27*REGBYTES(sp)`
106			`SREG x28, 28*REGBYTES(sp)`
107			`SREG x29, 29*REGBYTES(sp)`
108			`SREG x30, 30*REGBYTES(sp)`
109			`SREG x31, 31*REGBYTES(sp)`
110			`#endif // __RVE_EXT`
111
112			`csrr a0, mcause`
113			`csrr a1, mepc`
114			`mv a2, sp`
115			`jal handle_trap`
116
117			`LREG x1, 1*REGBYTES(sp)`
118			`LREG x2, 2*REGBYTES(sp)`
119			`LREG x3, 3*REGBYTES(sp)`
120			`LREG x4, 4*REGBYTES(sp)`
121			`LREG x5, 5*REGBYTES(sp)`
122			`LREG x6, 6*REGBYTES(sp)`
123			`LREG x7, 7*REGBYTES(sp)`
124			`LREG x8, 8*REGBYTES(sp)`
125			`LREG x9, 9*REGBYTES(sp)`
126			`LREG x10, 10*REGBYTES(sp)`
127			`LREG x11, 11*REGBYTES(sp)`
128			`LREG x12, 12*REGBYTES(sp)`
129			`LREG x13, 13*REGBYTES(sp)`
130			`LREG x14, 14*REGBYTES(sp)`
131			`LREG x15, 15*REGBYTES(sp)`
132			`#ifndef __RVE_EXT`
133			`LREG x16, 16*REGBYTES(sp)`
134			`LREG x17, 17*REGBYTES(sp)`
135			`LREG x18, 18*REGBYTES(sp)`
136			`LREG x19, 19*REGBYTES(sp)`
137			`LREG x20, 20*REGBYTES(sp)`
138			`LREG x21, 21*REGBYTES(sp)`
139			`LREG x22, 22*REGBYTES(sp)`
140			`LREG x23, 23*REGBYTES(sp)`
141			`LREG x24, 24*REGBYTES(sp)`
142			`LREG x25, 25*REGBYTES(sp)`
143			`LREG x26, 26*REGBYTES(sp)`
144			`LREG x27, 27*REGBYTES(sp)`
145			`LREG x28, 28*REGBYTES(sp)`
146			`LREG x29, 29*REGBYTES(sp)`
147			`LREG x30, 30*REGBYTES(sp)`
148			`LREG x31, 31*REGBYTES(sp)`
149			`#endif // __RVE_EXT`
150
151			`addi sp, sp, 272`
152			`mret`
153
154			`handle_trap:`
155			`j SIM_EXIT`
156
157			`// end of crt.S`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [crt_tcm.S] - Blame information for rev 22