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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [csr.h] - Blame information for rev 22

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/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
/// @file       <csr.h>
/// Architecture specific CSR's defs and inlines
 
#ifndef SCR_CSR_H
#define SCR_CSR_H
 
#include <stdint.h>
#include <stdbool.h>
 
#define __xstringify(s) __stringify(s)
#define __stringify(s) #s
 
#ifdef read_csr
#undef read_csr
#endif
 
#ifdef write_csr
#undef write_csr
#endif
 
#ifdef swap_csr
#undef swap_csr
#endif
 
#ifdef set_csr
#undef set_csr
#endif
 
#ifdef clear_csr
#undef clear_csr
#endif
 
#ifdef rdtime
#undef rdtime
#endif
 
#ifdef rdcycle
#undef rdcycle
#endif
 
#ifdef rdinstret
#undef rdinstret
#endif
 
#define read_csr(reg)                                               \
    ({                                                              \
        unsigned long __tmp;                                        \
        asm volatile ("csrr %0, " __xstringify(reg) : "=r"(__tmp)); \
        __tmp;                                                      \
    })
 
#define write_csr(reg, val)                                             \
    do {                                                                \
        if (__builtin_constant_p(val) && (val) == 0)                    \
            asm volatile ("csrw " __xstringify(reg) ", zero" ::);       \
        else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
            asm volatile ("csrw " __xstringify(reg) ", %0" :: "i"(val)); \
        else                                                            \
            asm volatile ("csrw " __xstringify(reg) ", %0" :: "r"(val)); \
    } while (0)
 
#define swap_csr(reg, val)                                              \
    ({                                                                  \
        unsigned long __tmp;                                            \
        if (__builtin_constant_p(val) && (val) == 0)                    \
            asm volatile ("csrrw %0, " __xstringify(reg) ", zero" :  "=r"(__tmp) :); \
        else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
            asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(val)); \
        else                                                            \
            asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(val)); \
        __tmp;                                                          \
    })
 
#define set_csr(reg, bit)                                               \
    ({                                                                  \
        unsigned long __tmp;                                            \
        if (__builtin_constant_p(bit) && (bit) < 32)                    \
            asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
        else                                                            \
            asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
        __tmp;                                                          \
    })
 
#define clear_csr(reg, bit)                                             \
    ({                                                                  \
        unsigned long __tmp;                                            \
        if (__builtin_constant_p(bit) && (bit) < 32)                    \
            asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \
        else                                                            \
            asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \
        __tmp;                                                          \
    })
 
#define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle)
#define rdinstret() read_csr(instret)
 
static inline unsigned long __attribute__((const)) cpuid()
{
  unsigned long res;
  asm ("csrr %0, mcpuid" : "=r"(res));
  return res;
}
 
static inline unsigned long __attribute__((const)) impid()
{
  unsigned long res;
  asm ("csrr %0, mimpid" : "=r"(res));
  return res;
}
 
#endif // SCR_CSR_H

Line No.	Rev	Author	Line
1	22	dinesha	`/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details`
2			`/// @file <csr.h>`
3			`/// Architecture specific CSR's defs and inlines`
4
5			`#ifndef SCR_CSR_H`
6			`#define SCR_CSR_H`
7
8			`#include <stdint.h>`
9			`#include <stdbool.h>`
10
11			`#define __xstringify(s) __stringify(s)`
12			`#define __stringify(s) #s`
13
14			`#ifdef read_csr`
15			`#undef read_csr`
16			`#endif`
17
18			`#ifdef write_csr`
19			`#undef write_csr`
20			`#endif`
21
22			`#ifdef swap_csr`
23			`#undef swap_csr`
24			`#endif`
25
26			`#ifdef set_csr`
27			`#undef set_csr`
28			`#endif`
29
30			`#ifdef clear_csr`
31			`#undef clear_csr`
32			`#endif`
33
34			`#ifdef rdtime`
35			`#undef rdtime`
36			`#endif`
37
38			`#ifdef rdcycle`
39			`#undef rdcycle`
40			`#endif`
41
42			`#ifdef rdinstret`
43			`#undef rdinstret`
44			`#endif`
45
46			`#define read_csr(reg) \`
47			`({ \`
48			`unsigned long __tmp; \`
49			`asm volatile ("csrr %0, " __xstringify(reg) : "=r"(__tmp)); \`
50			`__tmp; \`
51			`})`
52
53			`#define write_csr(reg, val) \`
54			`do { \`
55			`if (__builtin_constant_p(val) && (val) == 0) \`
56			`asm volatile ("csrw " __xstringify(reg) ", zero" ::); \`
57			`else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \`
58			`asm volatile ("csrw " __xstringify(reg) ", %0" :: "i"(val)); \`
59			`else \`
60			`asm volatile ("csrw " __xstringify(reg) ", %0" :: "r"(val)); \`
61			`} while (0)`
62
63			`#define swap_csr(reg, val) \`
64			`({ \`
65			`unsigned long __tmp; \`
66			`if (__builtin_constant_p(val) && (val) == 0) \`
67			`asm volatile ("csrrw %0, " __xstringify(reg) ", zero" : "=r"(__tmp) :); \`
68			`else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \`
69			`asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(val)); \`
70			`else \`
71			`asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(val)); \`
72			`__tmp; \`
73			`})`
74
75			`#define set_csr(reg, bit) \`
76			`({ \`
77			`unsigned long __tmp; \`
78			`if (__builtin_constant_p(bit) && (bit) < 32) \`
79			`asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \`
80			`else \`
81			`asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \`
82			`__tmp; \`
83			`})`
84
85			`#define clear_csr(reg, bit) \`
86			`({ \`
87			`unsigned long __tmp; \`
88			`if (__builtin_constant_p(bit) && (bit) < 32) \`
89			`asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \`
90			`else \`
91			`asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \`
92			`__tmp; \`
93			`})`
94
95			`#define rdtime() read_csr(time)`
96			`#define rdcycle() read_csr(cycle)`
97			`#define rdinstret() read_csr(instret)`
98
99			`static inline unsigned long __attribute__((const)) cpuid()`
100			`{`
101			`unsigned long res;`
102			`asm ("csrr %0, mcpuid" : "=r"(res));`
103			`return res;`
104			`}`
105
106			`static inline unsigned long __attribute__((const)) impid()`
107			`{`
108			`unsigned long res;`
109			`asm ("csrr %0, mimpid" : "=r"(res));`
110			`return res;`
111			`}`
112
113			`#endif // SCR_CSR_H`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [csr.h] - Blame information for rev 22