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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [link.ld] - Blame information for rev 22

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/*
* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
* @file       
* @brief      bare metal tests' linker script
*/
 
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
 
MEMORY {
  RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K
}
 
STACK_SIZE = 1024;
 
CL_SIZE = 32;
 
SECTIONS {
 
  /* code segment */
  .text.init 0 : {
    FILL(0);
    . = 0x100 - 12;
    SIM_EXIT = .;
    LONG(0x13);
    SIM_STOP = .;
    LONG(0x6F);
    LONG(-1);
    . = 0x100;
    PROVIDE(__TEXT_START__ = .);
    *(.text.init)
  } >RAM
 
  .text  : {
    *crt.o(.text .text.*)
    *(.text .text.*)
    *(sc_test_section)
    . = ALIGN(CL_SIZE);
     PROVIDE(__TEXT_END__ = .);
  } >RAM
 
  /* data segment */
  .data : {
    *(.data .data.*)
    . = ALIGN(CL_SIZE);
  } >RAM
 
  .sdata : {
    __global_pointer$ = . + 0x800;
    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
    *(.sdata .sdata.* .gnu.linkonce.s.*)
    . = ALIGN(CL_SIZE);
  } >RAM
 
  /* thread-local data segment */
  .tdata : {
    PROVIDE(_tls_data = .);
    PROVIDE(_tdata_begin = .);
    *(.tdata .tdata.*)
    PROVIDE(_tdata_end = .);
    . = ALIGN(CL_SIZE);
  } >RAM
 
  .tbss : {
    PROVIDE(__BSS_START__ = .);
    *(.tbss .tbss.*)
    . = ALIGN(CL_SIZE);
    PROVIDE(_tbss_end = .);
  } >RAM
 
  /* bss segment */
  .sbss : {
    *(.sbss .sbss.* .gnu.linkonce.sb.*)
    *(.scommon)
  } >RAM
 
  .bss : {
    *(.bss .bss.*)
    . = ALIGN(CL_SIZE);
    PROVIDE(__BSS_END__ = .);
  } >RAM
 
  _end = .;
  PROVIDE(__end = .);
 
  /* End of uninitalized data segement */
 
  .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : {
    FILL(0);
    PROVIDE(__STACK_START__ = .);
    . += STACK_SIZE;
    PROVIDE(__C_STACK_TOP__ = .);
    PROVIDE(__STACK_END__ = .);
  } >RAM
 
  /DISCARD/ : {
    *(.eh_frame .eh_frame.*)
  }
}

Line No.	Rev	Author	Line
1	22	dinesha	`/*`
2			`* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details`
3			`* @file`
4			`* @brief bare metal tests' linker script`
5			`*/`
6
7			`OUTPUT_ARCH( "riscv" )`
8			`ENTRY(_start)`
9
10			`MEMORY {`
11			`RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K`
12			`}`
13
14			`STACK_SIZE = 1024;`
15
16			`CL_SIZE = 32;`
17
18			`SECTIONS {`
19
20			`/* code segment */`
21			`.text.init 0 : {`
22			`FILL(0);`
23			`. = 0x100 - 12;`
24			`SIM_EXIT = .;`
25			`LONG(0x13);`
26			`SIM_STOP = .;`
27			`LONG(0x6F);`
28			`LONG(-1);`
29			`. = 0x100;`
30			`PROVIDE(__TEXT_START__ = .);`
31			`*(.text.init)`
32			`} >RAM`
33
34			`.text : {`
35			`crt.o(.text .text.)`
36			`(.text .text.)`
37			`*(sc_test_section)`
38			`. = ALIGN(CL_SIZE);`
39			`PROVIDE(__TEXT_END__ = .);`
40			`} >RAM`
41
42			`/* data segment */`
43			`.data : {`
44			`(.data .data.)`
45			`. = ALIGN(CL_SIZE);`
46			`} >RAM`
47
48			`.sdata : {`
49			`__global_pointer$ = . + 0x800;`
50			`(.srodata.cst16) (.srodata.cst8) (.srodata.cst4) (.srodata.cst2) (.srodata)`
51			`(.sdata .sdata. .gnu.linkonce.s.*)`
52			`. = ALIGN(CL_SIZE);`
53			`} >RAM`
54
55			`/* thread-local data segment */`
56			`.tdata : {`
57			`PROVIDE(_tls_data = .);`
58			`PROVIDE(_tdata_begin = .);`
59			`(.tdata .tdata.)`
60			`PROVIDE(_tdata_end = .);`
61			`. = ALIGN(CL_SIZE);`
62			`} >RAM`
63
64			`.tbss : {`
65			`PROVIDE(__BSS_START__ = .);`
66			`(.tbss .tbss.)`
67			`. = ALIGN(CL_SIZE);`
68			`PROVIDE(_tbss_end = .);`
69			`} >RAM`
70
71			`/* bss segment */`
72			`.sbss : {`
73			`(.sbss .sbss. .gnu.linkonce.sb.*)`
74			`*(.scommon)`
75			`} >RAM`
76
77			`.bss : {`
78			`(.bss .bss.)`
79			`. = ALIGN(CL_SIZE);`
80			`PROVIDE(__BSS_END__ = .);`
81			`} >RAM`
82
83			`_end = .;`
84			`PROVIDE(__end = .);`
85
86			`/* End of uninitalized data segement */`
87
88			`.stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : {`
89			`FILL(0);`
90			`PROVIDE(__STACK_START__ = .);`
91			`. += STACK_SIZE;`
92			`PROVIDE(__C_STACK_TOP__ = .);`
93			`PROVIDE(__STACK_END__ = .);`
94			`} >RAM`
95
96			`/DISCARD/ : {`
97			`(.eh_frame .eh_frame.)`
98			`}`
99			`}`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [link.ld] - Blame information for rev 22