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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [link_tcm.ld] - Blame information for rev 22

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/*
* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
* @file       
* @brief      bare metal tests' linker script
*/
 
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
 
MEMORY {
  RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K
  TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 64K
}
 
STACK_SIZE = 1024;
 
CL_SIZE = 32;
 
SECTIONS {
 
  /* code segment */
  .text.init ORIGIN(RAM) : {
    FILL(0);
    . = 0x100 - 12;
    SIM_EXIT = .;
    LONG(0x13);
    SIM_STOP = .;
    LONG(0x6F);
    LONG(-1);
    . = 0x100;
    *crt_tcm.o(.text .text.*)
    *(.text.init)
    . = ALIGN(CL_SIZE);
  } >RAM
 
  __reloc_start = .;
 
  .text : {
    PROVIDE(__TEXT_START__ = .);
    *(.text .text.*)
    *(sc_test_section)
    . = ALIGN(CL_SIZE);
     PROVIDE(__TEXT_END__ = .);
  } >TCM AT>RAM
 
  .rodata ALIGN(CL_SIZE) : {
    __global_pointer$ = . + 0x800;
    *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*)
    . = ALIGN(CL_SIZE);
    LONG(0x13);
    . = ALIGN(CL_SIZE);
  } >TCM AT>RAM
 
 
  /* data segment */
  .data ALIGN(CL_SIZE) : {
    PROVIDE(__DATA_START__ = .);
    *(.data .data.*)
    . = ALIGN(CL_SIZE);
  } >TCM AT>RAM
 
 
  .sdata ALIGN(CL_SIZE) : {
    *(.sdata .sdata.* .gnu.linkonce.s.*)
    . = ALIGN(CL_SIZE);
    PROVIDE(__DATA_END__ = .);
  } >TCM AT>RAM
 
  /* thread-local data segment */
  .tdata ALIGN(CL_SIZE) : {
    PROVIDE(_tls_data = .);
    PROVIDE(_tdata_begin = .);
    *(.tdata .tdata.*)
    PROVIDE(_tdata_end = .);
    . = ALIGN(CL_SIZE);
  } >TCM AT>RAM
 
  .tbss ALIGN(CL_SIZE) : {
    PROVIDE(_tbss_begin = .);
    *(.tbss .tbss.*)
    . = ALIGN(CL_SIZE);
    PROVIDE(_tbss_end = .);
  } >TCM AT>RAM
 
  /* bss segment */
  .sbss ALIGN(CL_SIZE) : {
    PROVIDE(__BSS_START__ = .);
    *(.sbss .sbss.* .gnu.linkonce.sb.*)
    *(.scommon)
    . = ALIGN(CL_SIZE);
  } >TCM AT>RAM
 
  .bss ALIGN(CL_SIZE) : {
    *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
    . = ALIGN(CL_SIZE);
    PROVIDE(__BSS_END__ = .);
  } >TCM AT>RAM
 
  _end = .;
  PROVIDE(__end = .);
 
  /* End of uninitalized data segement */
 
  .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {
    PROVIDE(__STACK_START__ = .);
    . += STACK_SIZE;
    PROVIDE(__C_STACK_TOP__ = .);
    PROVIDE(__STACK_END__ = .);
  } >TCM
 
  /DISCARD/ : {
    *(.eh_frame .eh_frame.*)
  }
}

Line No.	Rev	Author	Line
1	22	dinesha	`/*`
2			`* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details`
3			`* @file`
4			`* @brief bare metal tests' linker script`
5			`*/`
6
7			`OUTPUT_ARCH( "riscv" )`
8			`ENTRY(_start)`
9
10			`MEMORY {`
11			`RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K`
12			`TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 64K`
13			`}`
14
15			`STACK_SIZE = 1024;`
16
17			`CL_SIZE = 32;`
18
19			`SECTIONS {`
20
21			`/* code segment */`
22			`.text.init ORIGIN(RAM) : {`
23			`FILL(0);`
24			`. = 0x100 - 12;`
25			`SIM_EXIT = .;`
26			`LONG(0x13);`
27			`SIM_STOP = .;`
28			`LONG(0x6F);`
29			`LONG(-1);`
30			`. = 0x100;`
31			`crt_tcm.o(.text .text.)`
32			`*(.text.init)`
33			`. = ALIGN(CL_SIZE);`
34			`} >RAM`
35
36			`__reloc_start = .;`
37
38			`.text : {`
39			`PROVIDE(__TEXT_START__ = .);`
40			`(.text .text.)`
41			`*(sc_test_section)`
42			`. = ALIGN(CL_SIZE);`
43			`PROVIDE(__TEXT_END__ = .);`
44			`} >TCM AT>RAM`
45
46			`.rodata ALIGN(CL_SIZE) : {`
47			`__global_pointer$ = . + 0x800;`
48			`(.rodata) (.rodata.) (.gnu.linkonce.r.*)`
49			`. = ALIGN(CL_SIZE);`
50			`LONG(0x13);`
51			`. = ALIGN(CL_SIZE);`
52			`} >TCM AT>RAM`
53
54
55			`/* data segment */`
56			`.data ALIGN(CL_SIZE) : {`
57			`PROVIDE(__DATA_START__ = .);`
58			`(.data .data.)`
59			`. = ALIGN(CL_SIZE);`
60			`} >TCM AT>RAM`
61
62
63			`.sdata ALIGN(CL_SIZE) : {`
64			`(.sdata .sdata. .gnu.linkonce.s.*)`
65			`. = ALIGN(CL_SIZE);`
66			`PROVIDE(__DATA_END__ = .);`
67			`} >TCM AT>RAM`
68
69			`/* thread-local data segment */`
70			`.tdata ALIGN(CL_SIZE) : {`
71			`PROVIDE(_tls_data = .);`
72			`PROVIDE(_tdata_begin = .);`
73			`(.tdata .tdata.)`
74			`PROVIDE(_tdata_end = .);`
75			`. = ALIGN(CL_SIZE);`
76			`} >TCM AT>RAM`
77
78			`.tbss ALIGN(CL_SIZE) : {`
79			`PROVIDE(_tbss_begin = .);`
80			`(.tbss .tbss.)`
81			`. = ALIGN(CL_SIZE);`
82			`PROVIDE(_tbss_end = .);`
83			`} >TCM AT>RAM`
84
85			`/* bss segment */`
86			`.sbss ALIGN(CL_SIZE) : {`
87			`PROVIDE(__BSS_START__ = .);`
88			`(.sbss .sbss. .gnu.linkonce.sb.*)`
89			`*(.scommon)`
90			`. = ALIGN(CL_SIZE);`
91			`} >TCM AT>RAM`
92
93			`.bss ALIGN(CL_SIZE) : {`
94			`(.dynbss) (.bss .bss.* .gnu.linkonce.b.) (COMMON)`
95			`. = ALIGN(CL_SIZE);`
96			`PROVIDE(__BSS_END__ = .);`
97			`} >TCM AT>RAM`
98
99			`_end = .;`
100			`PROVIDE(__end = .);`
101
102			`/* End of uninitalized data segement */`
103
104			`.stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : {`
105			`PROVIDE(__STACK_START__ = .);`
106			`. += STACK_SIZE;`
107			`PROVIDE(__C_STACK_TOP__ = .);`
108			`PROVIDE(__STACK_END__ = .);`
109			`} >TCM`
110
111			`/DISCARD/ : {`
112			`(.eh_frame .eh_frame.)`
113			`}`
114			`}`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [link_tcm.ld] - Blame information for rev 22