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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [reloc.h] - Blame information for rev 22

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Line No. Rev Author Line
1 22 dinesha 
#ifndef RELOC_H
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#define RELOC_H
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#if (TCM == 1)
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#define RELOC_PROC              \
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    la    a0, __reloc_start;    \
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    la    a1, __TEXT_START__;   \
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    la    a2, __DATA_END__;     \
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    beq   a0, a1, 21f;          \
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    j     2f;                   \
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1:  lw    a3, 0(a0);            \
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    sw    a3, 0(a1);            \
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    add   a0, a0, 4;            \
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    add   a1, a1, 4;            \
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2:  bne   a1, a2, 1b;           \
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    /* clear bss */             \
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    la    a2, __BSS_START__;    \
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21: la    a1, __BSS_END__;      \
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    j     4f;                   \
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3:  sw    zero, 0(a2);          \
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    add   a2, a2, 4;            \
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4:  bne   a1, a2, 3b;           \
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    /* init stack */            \
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    la    sp, __C_STACK_TOP__;  \
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    /* init hart0 TLS */        \
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    la    a0, _tdata_begin;     \
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    la    a2, _tbss_end;        \
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    sub   a1, a2, a0;           \
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    la    a4, __STACK_START__;  \
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    sub   tp, a4, a1;
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#else  // #if TCM
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#define RELOC_PROC
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#endif  // #else #if TCM
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#endif  //

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