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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [sc_test.h] - Blame information for rev 22

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1 22 dinesha
/// Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details
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/// @file       <sc_test.h>
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///
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#ifndef SC_TEST_H
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#define SC_TEST_H
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#if defined(__ASSEMBLER__)
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.altmacro
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.macro zero_int_reg regn
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mv   x\regn, zero
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.endm
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.macro zero_int_regs reg_first, reg_last
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.set regn, \reg_first
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.rept \reg_last - \reg_first + 1
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zero_int_reg %(regn)
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.set regn, regn+1
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.endr
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.endm
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#define report_results(result) \
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li  a0, result;  \
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la t0, sc_exit;  \
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jr       t0;
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.pushsection sc_test_section, "ax"
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sc_exit: la t0, SIM_EXIT; jr t0;
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.balign 32
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.popsection
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#define sc_pass report_results(0x0)
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#define sc_fail report_results(0x1)
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#else
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extern void sc_exit(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3)
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    __attribute__ ((noinline, noreturn));
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static inline void  __attribute__ ((noreturn))
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report_results(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3)
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{
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    sc_exit(result, res0, res1, res2, res3);
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}
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#endif
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#endif // SC_TEST_H

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