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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [scr1_specific.h] - Blame information for rev 22

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#ifndef __SCR1__SPECIFIC
#define __SCR1__SPECIFIC
 
#define mcounten        0x7E0
 
// Memory-mapped registers
#define mtime_ctrl      0x00490000
#define mtime_div       0x00490004
#define mtime           0x00490008
#define mtimeh          0x0049000C
#define mtimecmp        0x00490010
#define mtimecmph       0x00490014
 
#define SCR1_MTIME_CTRL_EN          0
#define SCR1_MTIME_CTRL_CLKSRC      1
 
#define SCR1_MTIME_CTRL_WR_MASK     0x3
#define SCR1_MTIME_DIV_WR_MASK      0x3FF
 
#endif // _SCR1__SPECIFIC

Line No.	Rev	Author	Line
1	22	dinesha	`#ifndef __SCR1__SPECIFIC`
2			`#define __SCR1__SPECIFIC`
3
4			`#define mcounten 0x7E0`
5
6			`// Memory-mapped registers`
7			`#define mtime_ctrl 0x00490000`
8			`#define mtime_div 0x00490004`
9			`#define mtime 0x00490008`
10			`#define mtimeh 0x0049000C`
11			`#define mtimecmp 0x00490010`
12			`#define mtimecmph 0x00490014`
13
14			`#define SCR1_MTIME_CTRL_EN 0`
15			`#define SCR1_MTIME_CTRL_CLKSRC 1`
16
17			`#define SCR1_MTIME_CTRL_WR_MASK 0x3`
18			`#define SCR1_MTIME_DIV_WR_MASK 0x3FF`
19
20			`#endif // _SCR1__SPECIFIC`

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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [sim/] [tests/] [common/] [scr1_specific.h] - Blame information for rev 22