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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief Instruction Decoder Unit (IDU)
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///
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//------------------------------------------------------------------------------
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//
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// Functionality:
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// - Decodes the instruction and creates the appropriate control signals for EXU
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//
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// Structure:
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// - Instruction decoder
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// - IDU <-> IFU i/f
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// - IDU <-> EXU i/f
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//
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//------------------------------------------------------------------------------
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`include "scr1_memif.svh"
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`include "scr1_arch_types.svh"
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`include "scr1_riscv_isa_decoding.svh"
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`include "scr1_arch_description.svh"
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module scr1_pipe_idu
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(
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`ifdef SCR1_TRGT_SIMULATION
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input logic rst_n, // IDU reset
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input logic clk, // IDU clock
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`endif // SCR1_TRGT_SIMULATION
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// IFU <-> IDU interface
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output logic idu2ifu_rdy_o, // IDU ready for new data
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input logic [`SCR1_IMEM_DWIDTH-1:0] ifu2idu_instr_i, // IFU instruction
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input logic ifu2idu_imem_err_i, // Instruction access fault exception
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input logic ifu2idu_err_rvi_hi_i, // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
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input logic ifu2idu_vd_i, // IFU request
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// IDU <-> EXU interface
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output logic idu2exu_req_o, // IDU request
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output type_scr1_exu_cmd_s idu2exu_cmd_o, // IDU command
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output logic idu2exu_use_rs1_o, // Instruction uses rs1
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output logic idu2exu_use_rs2_o, // Instruction uses rs2
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output logic idu2exu_use_rd_o, // Instruction uses rd
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output logic idu2exu_use_imm_o, // Instruction uses immediate
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input logic exu2idu_rdy_i // EXU ready for new data
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);
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//-------------------------------------------------------------------------------
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// Local parameters declaration
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//-------------------------------------------------------------------------------
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localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_ZERO_ADDR = 5'd0;
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localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_RA_ADDR = 5'd1;
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localparam [SCR1_GPR_FIELD_WIDTH-1:0] SCR1_MPRF_SP_ADDR = 5'd2;
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//-------------------------------------------------------------------------------
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// Local signals declaration
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//-------------------------------------------------------------------------------
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logic [`SCR1_IMEM_DWIDTH-1:0] instr;
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logic [1:0] instr_type;
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logic [6:2] rvi_opcode;
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logic rvi_illegal;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] funct12;
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logic [4:0] shamt;
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`ifdef SCR1_RVC_EXT
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logic rvc_illegal;
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`endif // SCR1_RVC_EXT
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`ifdef SCR1_RVE_EXT
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logic rve_illegal;
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`endif // SCR1_RVE_EXT
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//-------------------------------------------------------------------------------
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// Instruction decoding
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//-------------------------------------------------------------------------------
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assign idu2ifu_rdy_o = exu2idu_rdy_i;
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assign idu2exu_req_o = ifu2idu_vd_i;
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assign instr = ifu2idu_instr_i;
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// RVI / RVC
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assign instr_type = instr[1:0];
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// RVI / RVC fields
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assign rvi_opcode = instr[6:2]; // RVI
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assign funct3 = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
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assign funct7 = instr[31:25]; // RVI
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assign funct12 = instr[31:20]; // RVI (SYSTEM)
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assign shamt = instr[24:20]; // RVI
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// RV32I(MC) decode
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always_comb begin
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// Defaults
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idu2exu_cmd_o.instr_rvc = 1'b0;
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idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
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idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_NONE;
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idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
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idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_NONE;
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idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
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idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_NONE;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_NONE;
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idu2exu_cmd_o.jump_req = 1'b0;
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idu2exu_cmd_o.branch_req = 1'b0;
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idu2exu_cmd_o.mret_req = 1'b0;
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idu2exu_cmd_o.fencei_req = 1'b0;
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idu2exu_cmd_o.wfi_req = 1'b0;
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idu2exu_cmd_o.rs1_addr = '0;
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idu2exu_cmd_o.rs2_addr = '0;
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idu2exu_cmd_o.rd_addr = '0;
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idu2exu_cmd_o.imm = '0;
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idu2exu_cmd_o.exc_req = 1'b0;
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idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_INSTR_MISALIGN;
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// Clock gating
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idu2exu_use_rs1_o = 1'b0;
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idu2exu_use_rs2_o = 1'b0;
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idu2exu_use_rd_o = 1'b0;
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idu2exu_use_imm_o = 1'b0;
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rvi_illegal = 1'b0;
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`ifdef SCR1_RVE_EXT
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rve_illegal = 1'b0;
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`endif // SCR1_RVE_EXT
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`ifdef SCR1_RVC_EXT
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rvc_illegal = 1'b0;
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`endif // SCR1_RVC_EXT
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// Check for IMEM access fault
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if (ifu2idu_imem_err_i) begin
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idu2exu_cmd_o.exc_req = 1'b1;
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idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_INSTR_ACCESS_FAULT;
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idu2exu_cmd_o.instr_rvc = ifu2idu_err_rvi_hi_i;
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end else begin // no imem fault
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case (instr_type)
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SCR1_INSTR_RVI : begin
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idu2exu_cmd_o.rs1_addr = instr[19:15];
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idu2exu_cmd_o.rs2_addr = instr[24:20];
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idu2exu_cmd_o.rd_addr = instr[11:7];
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case (rvi_opcode)
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SCR1_OPCODE_AUIPC : begin
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idu2exu_use_rd_o = 1'b1;
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idu2exu_use_imm_o = 1'b1;
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idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_SUM2;
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idu2exu_cmd_o.imm = {instr[31:12], 12'b0};
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`ifdef SCR1_RVE_EXT
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if (instr[11]) rve_illegal = 1'b1;
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`endif // SCR1_RVE_EXT
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end // SCR1_OPCODE_AUIPC
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SCR1_OPCODE_LUI : begin
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idu2exu_use_rd_o = 1'b1;
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idu2exu_use_imm_o = 1'b1;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IMM;
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idu2exu_cmd_o.imm = {instr[31:12], 12'b0};
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`ifdef SCR1_RVE_EXT
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if (instr[11]) rve_illegal = 1'b1;
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`endif // SCR1_RVE_EXT
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end // SCR1_OPCODE_LUI
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SCR1_OPCODE_JAL : begin
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idu2exu_use_rd_o = 1'b1;
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idu2exu_use_imm_o = 1'b1;
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idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
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idu2exu_cmd_o.jump_req = 1'b1;
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idu2exu_cmd_o.imm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
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`ifdef SCR1_RVE_EXT
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if (instr[11]) rve_illegal = 1'b1;
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`endif // SCR1_RVE_EXT
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end // SCR1_OPCODE_JAL
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SCR1_OPCODE_LOAD : begin
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idu2exu_use_rs1_o = 1'b1;
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idu2exu_use_rd_o = 1'b1;
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idu2exu_use_imm_o = 1'b1;
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idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_LSU;
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idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:20]};
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case (funct3)
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3'b000 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LB;
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3'b001 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LH;
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3'b010 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LW;
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3'b100 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LBU;
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3'b101 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LHU;
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default : rvi_illegal = 1'b1;
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endcase // funct3
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`ifdef SCR1_RVE_EXT
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if (instr[11] | instr[19]) rve_illegal = 1'b1;
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`endif // SCR1_RVE_EXT
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end // SCR1_OPCODE_LOAD
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SCR1_OPCODE_STORE : begin
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idu2exu_use_rs1_o = 1'b1;
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idu2exu_use_rs2_o = 1'b1;
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idu2exu_use_imm_o = 1'b1;
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idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
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idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:25], instr[11:7]};
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case (funct3)
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3'b000 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SB;
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3'b001 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SH;
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3'b010 : idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SW;
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default : rvi_illegal = 1'b1;
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endcase // funct3
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`ifdef SCR1_RVE_EXT
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if (instr[19] | instr[24]) rve_illegal = 1'b1;
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`endif // SCR1_RVE_EXT
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end // SCR1_OPCODE_STORE
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SCR1_OPCODE_OP : begin
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idu2exu_use_rs1_o = 1'b1;
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idu2exu_use_rs2_o = 1'b1;
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idu2exu_use_rd_o = 1'b1;
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idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
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case (funct7)
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7'b0000000 : begin
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case (funct3)
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3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
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3'b001 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SLL;
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3'b010 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LT;
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3'b011 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LTU;
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3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_XOR;
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3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRL;
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3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_OR;
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3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND;
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endcase // funct3
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end // 7'b0000000
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7'b0100000 : begin
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case (funct3)
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3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB;
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3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRA;
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default : rvi_illegal = 1'b1;
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endcase // funct3
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end // 7'b0100000
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`ifdef SCR1_RVM_EXT
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7'b0000001 : begin
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case (funct3)
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3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MUL;
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3'b001 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MULH;
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3'b010 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MULHSU;
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3'b011 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_MULHU;
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3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_DIV;
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3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_DIVU;
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3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_REM;
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3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_REMU;
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endcase // funct3
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end // 7'b0000001
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`endif // SCR1_RVM_EXT
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default : rvi_illegal = 1'b1;
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endcase // funct7
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`ifdef SCR1_RVE_EXT
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if (instr[11] | instr[19] | instr[24]) rve_illegal = 1'b1;
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`endif // SCR1_RVE_EXT
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end // SCR1_OPCODE_OP
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SCR1_OPCODE_OP_IMM : begin
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idu2exu_use_rs1_o = 1'b1;
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idu2exu_use_rd_o = 1'b1;
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idu2exu_use_imm_o = 1'b1;
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idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:20]};
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idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
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idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
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|
|
case (funct3)
|
| 267 |
|
|
3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD; // ADDI
|
| 268 |
|
|
3'b010 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LT; // SLTI
|
| 269 |
|
|
3'b011 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LTU; // SLTIU
|
| 270 |
|
|
3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_XOR; // XORI
|
| 271 |
|
|
3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_OR; // ORI
|
| 272 |
|
|
3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND; // ANDI
|
| 273 |
|
|
3'b001 : begin
|
| 274 |
|
|
case (funct7)
|
| 275 |
|
|
7'b0000000 : begin
|
| 276 |
|
|
// SLLI
|
| 277 |
|
|
idu2exu_cmd_o.imm = `SCR1_XLEN'(shamt); // zero-extend
|
| 278 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SLL;
|
| 279 |
|
|
end
|
| 280 |
|
|
default : rvi_illegal = 1'b1;
|
| 281 |
|
|
endcase // funct7
|
| 282 |
|
|
end
|
| 283 |
|
|
3'b101 : begin
|
| 284 |
|
|
case (funct7)
|
| 285 |
|
|
7'b0000000 : begin
|
| 286 |
|
|
// SRLI
|
| 287 |
|
|
idu2exu_cmd_o.imm = `SCR1_XLEN'(shamt); // zero-extend
|
| 288 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRL;
|
| 289 |
|
|
end
|
| 290 |
|
|
7'b0100000 : begin
|
| 291 |
|
|
// SRAI
|
| 292 |
|
|
idu2exu_cmd_o.imm = `SCR1_XLEN'(shamt); // zero-extend
|
| 293 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRA;
|
| 294 |
|
|
end
|
| 295 |
|
|
default : rvi_illegal = 1'b1;
|
| 296 |
|
|
endcase // funct7
|
| 297 |
|
|
end
|
| 298 |
|
|
endcase // funct3
|
| 299 |
|
|
`ifdef SCR1_RVE_EXT
|
| 300 |
|
|
if (instr[11] | instr[19]) rve_illegal = 1'b1;
|
| 301 |
|
|
`endif // SCR1_RVE_EXT
|
| 302 |
|
|
end // SCR1_OPCODE_OP_IMM
|
| 303 |
|
|
|
| 304 |
|
|
SCR1_OPCODE_MISC_MEM : begin
|
| 305 |
|
|
case (funct3)
|
| 306 |
|
|
3'b000 : begin
|
| 307 |
|
|
if (~|{instr[31:28], instr[19:15], instr[11:7]}) begin
|
| 308 |
|
|
// FENCE = NOP
|
| 309 |
|
|
end
|
| 310 |
|
|
else rvi_illegal = 1'b1;
|
| 311 |
|
|
end
|
| 312 |
|
|
3'b001 : begin
|
| 313 |
|
|
if (~|{instr[31:15], instr[11:7]}) begin
|
| 314 |
|
|
// FENCE.I
|
| 315 |
|
|
idu2exu_cmd_o.fencei_req = 1'b1;
|
| 316 |
|
|
end
|
| 317 |
|
|
else rvi_illegal = 1'b1;
|
| 318 |
|
|
end
|
| 319 |
|
|
default : rvi_illegal = 1'b1;
|
| 320 |
|
|
endcase // funct3
|
| 321 |
|
|
end // SCR1_OPCODE_MISC_MEM
|
| 322 |
|
|
|
| 323 |
|
|
SCR1_OPCODE_BRANCH : begin
|
| 324 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 325 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 326 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 327 |
|
|
idu2exu_cmd_o.imm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
|
| 328 |
|
|
idu2exu_cmd_o.branch_req = 1'b1;
|
| 329 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
|
| 330 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 331 |
|
|
case (funct3)
|
| 332 |
|
|
3'b000 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_EQ;
|
| 333 |
|
|
3'b001 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_NE;
|
| 334 |
|
|
3'b100 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LT;
|
| 335 |
|
|
3'b101 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_GE;
|
| 336 |
|
|
3'b110 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_LTU;
|
| 337 |
|
|
3'b111 : idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_GEU;
|
| 338 |
|
|
default : rvi_illegal = 1'b1;
|
| 339 |
|
|
endcase // funct3
|
| 340 |
|
|
`ifdef SCR1_RVE_EXT
|
| 341 |
|
|
if (instr[19] | instr[24]) rve_illegal = 1'b1;
|
| 342 |
|
|
`endif // SCR1_RVE_EXT
|
| 343 |
|
|
end // SCR1_OPCODE_BRANCH
|
| 344 |
|
|
|
| 345 |
|
|
SCR1_OPCODE_JALR : begin
|
| 346 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 347 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 348 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 349 |
|
|
case (funct3)
|
| 350 |
|
|
3'b000 : begin
|
| 351 |
|
|
// JALR
|
| 352 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 353 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
|
| 354 |
|
|
idu2exu_cmd_o.jump_req = 1'b1;
|
| 355 |
|
|
idu2exu_cmd_o.imm = {{21{instr[31]}}, instr[30:20]};
|
| 356 |
|
|
end
|
| 357 |
|
|
default : rvi_illegal = 1'b1;
|
| 358 |
|
|
endcase
|
| 359 |
|
|
`ifdef SCR1_RVE_EXT
|
| 360 |
|
|
if (instr[11] | instr[19]) rve_illegal = 1'b1;
|
| 361 |
|
|
`endif // SCR1_RVE_EXT
|
| 362 |
|
|
end // SCR1_OPCODE_JALR
|
| 363 |
|
|
|
| 364 |
|
|
SCR1_OPCODE_SYSTEM : begin
|
| 365 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 366 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 367 |
|
|
idu2exu_cmd_o.imm = `SCR1_XLEN'({funct3, instr[31:20]}); // {funct3, CSR address}
|
| 368 |
|
|
case (funct3)
|
| 369 |
|
|
3'b000 : begin
|
| 370 |
|
|
idu2exu_use_rd_o = 1'b0;
|
| 371 |
|
|
idu2exu_use_imm_o = 1'b0;
|
| 372 |
|
|
case ({instr[19:15], instr[11:7]})
|
| 373 |
|
|
10'd0 : begin
|
| 374 |
|
|
case (funct12)
|
| 375 |
|
|
12'h000 : begin
|
| 376 |
|
|
// ECALL
|
| 377 |
|
|
idu2exu_cmd_o.exc_req = 1'b1;
|
| 378 |
|
|
idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_ECALL_M;
|
| 379 |
|
|
end
|
| 380 |
|
|
12'h001 : begin
|
| 381 |
|
|
// EBREAK
|
| 382 |
|
|
idu2exu_cmd_o.exc_req = 1'b1;
|
| 383 |
|
|
idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_BREAKPOINT;
|
| 384 |
|
|
end
|
| 385 |
|
|
12'h302 : begin
|
| 386 |
|
|
// MRET
|
| 387 |
|
|
idu2exu_cmd_o.mret_req = 1'b1;
|
| 388 |
|
|
end
|
| 389 |
|
|
12'h105 : begin
|
| 390 |
|
|
// WFI
|
| 391 |
|
|
idu2exu_cmd_o.wfi_req = 1'b1;
|
| 392 |
|
|
end
|
| 393 |
|
|
default : rvi_illegal = 1'b1;
|
| 394 |
|
|
endcase // funct12
|
| 395 |
|
|
end
|
| 396 |
|
|
default : rvi_illegal = 1'b1;
|
| 397 |
|
|
endcase // {instr[19:15], instr[11:7]}
|
| 398 |
|
|
end
|
| 399 |
|
|
3'b001 : begin
|
| 400 |
|
|
// CSRRW
|
| 401 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 402 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
|
| 403 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_WRITE;
|
| 404 |
|
|
idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
|
| 405 |
|
|
`ifdef SCR1_RVE_EXT
|
| 406 |
|
|
if (instr[11] | instr[19]) rve_illegal = 1'b1;
|
| 407 |
|
|
`endif // SCR1_RVE_EXT
|
| 408 |
|
|
end
|
| 409 |
|
|
3'b010 : begin
|
| 410 |
|
|
// CSRRS
|
| 411 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 412 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
|
| 413 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_SET;
|
| 414 |
|
|
idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
|
| 415 |
|
|
`ifdef SCR1_RVE_EXT
|
| 416 |
|
|
if (instr[11] | instr[19]) rve_illegal = 1'b1;
|
| 417 |
|
|
`endif // SCR1_RVE_EXT
|
| 418 |
|
|
end
|
| 419 |
|
|
3'b011 : begin
|
| 420 |
|
|
// CSRRC
|
| 421 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 422 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
|
| 423 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_CLEAR;
|
| 424 |
|
|
idu2exu_cmd_o.csr_op = SCR1_CSR_OP_REG;
|
| 425 |
|
|
`ifdef SCR1_RVE_EXT
|
| 426 |
|
|
if (instr[11] | instr[19]) rve_illegal = 1'b1;
|
| 427 |
|
|
`endif // SCR1_RVE_EXT
|
| 428 |
|
|
end
|
| 429 |
|
|
3'b101 : begin
|
| 430 |
|
|
// CSRRWI
|
| 431 |
|
|
idu2exu_use_rs1_o = 1'b1; // zimm
|
| 432 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
|
| 433 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_WRITE;
|
| 434 |
|
|
idu2exu_cmd_o.csr_op = SCR1_CSR_OP_IMM;
|
| 435 |
|
|
`ifdef SCR1_RVE_EXT
|
| 436 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 437 |
|
|
`endif // SCR1_RVE_EXT
|
| 438 |
|
|
end
|
| 439 |
|
|
3'b110 : begin
|
| 440 |
|
|
// CSRRSI
|
| 441 |
|
|
idu2exu_use_rs1_o = 1'b1; // zimm
|
| 442 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
|
| 443 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_SET;
|
| 444 |
|
|
idu2exu_cmd_o.csr_op = SCR1_CSR_OP_IMM;
|
| 445 |
|
|
`ifdef SCR1_RVE_EXT
|
| 446 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 447 |
|
|
`endif // SCR1_RVE_EXT
|
| 448 |
|
|
end
|
| 449 |
|
|
3'b111 : begin
|
| 450 |
|
|
// CSRRCI
|
| 451 |
|
|
idu2exu_use_rs1_o = 1'b1; // zimm
|
| 452 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_CSR;
|
| 453 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_CLEAR;
|
| 454 |
|
|
idu2exu_cmd_o.csr_op = SCR1_CSR_OP_IMM;
|
| 455 |
|
|
`ifdef SCR1_RVE_EXT
|
| 456 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 457 |
|
|
`endif // SCR1_RVE_EXT
|
| 458 |
|
|
end
|
| 459 |
|
|
default : rvi_illegal = 1'b1;
|
| 460 |
|
|
endcase // funct3
|
| 461 |
|
|
end // SCR1_OPCODE_SYSTEM
|
| 462 |
|
|
|
| 463 |
|
|
default : begin
|
| 464 |
|
|
rvi_illegal = 1'b1;
|
| 465 |
|
|
end
|
| 466 |
|
|
endcase // rvi_opcode
|
| 467 |
|
|
end // SCR1_INSTR_RVI
|
| 468 |
|
|
|
| 469 |
|
|
`ifdef SCR1_RVC_EXT
|
| 470 |
|
|
|
| 471 |
|
|
// Quadrant 0
|
| 472 |
|
|
SCR1_INSTR_RVC0 : begin
|
| 473 |
|
|
idu2exu_cmd_o.instr_rvc = 1'b1;
|
| 474 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 475 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 476 |
|
|
case (funct3)
|
| 477 |
|
|
3'b000 : begin
|
| 478 |
|
|
if (~|instr[12:5]) rvc_illegal = 1'b1;
|
| 479 |
|
|
// C.ADDI4SPN
|
| 480 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 481 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
|
| 482 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 483 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 484 |
|
|
idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
|
| 485 |
|
|
idu2exu_cmd_o.rd_addr = {2'b01, instr[4:2]};
|
| 486 |
|
|
idu2exu_cmd_o.imm = {22'd0, instr[10:7], instr[12:11], instr[5], instr[6], 2'b00};
|
| 487 |
|
|
end
|
| 488 |
|
|
3'b010 : begin
|
| 489 |
|
|
// C.LW
|
| 490 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 491 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 492 |
|
|
idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LW;
|
| 493 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_LSU;
|
| 494 |
|
|
idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
|
| 495 |
|
|
idu2exu_cmd_o.rd_addr = {2'b01, instr[4:2]};
|
| 496 |
|
|
idu2exu_cmd_o.imm = {25'd0, instr[5], instr[12:10], instr[6], 2'b00};
|
| 497 |
|
|
end
|
| 498 |
|
|
3'b110 : begin
|
| 499 |
|
|
// C.SW
|
| 500 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 501 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 502 |
|
|
idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SW;
|
| 503 |
|
|
idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
|
| 504 |
|
|
idu2exu_cmd_o.rs2_addr = {2'b01, instr[4:2]};
|
| 505 |
|
|
idu2exu_cmd_o.imm = {25'd0, instr[5], instr[12:10], instr[6], 2'b00};
|
| 506 |
|
|
end
|
| 507 |
|
|
default : begin
|
| 508 |
|
|
rvc_illegal = 1'b1;
|
| 509 |
|
|
end
|
| 510 |
|
|
endcase // funct3
|
| 511 |
|
|
end // Quadrant 0
|
| 512 |
|
|
|
| 513 |
|
|
// Quadrant 1
|
| 514 |
|
|
SCR1_INSTR_RVC1 : begin
|
| 515 |
|
|
idu2exu_cmd_o.instr_rvc = 1'b1;
|
| 516 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 517 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 518 |
|
|
case (funct3)
|
| 519 |
|
|
3'b000 : begin
|
| 520 |
|
|
// C.ADDI / C.NOP
|
| 521 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 522 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
|
| 523 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 524 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 525 |
|
|
idu2exu_cmd_o.rs1_addr = instr[11:7];
|
| 526 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 527 |
|
|
idu2exu_cmd_o.imm = {{27{instr[12]}}, instr[6:2]};
|
| 528 |
|
|
`ifdef SCR1_RVE_EXT
|
| 529 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 530 |
|
|
`endif // SCR1_RVE_EXT
|
| 531 |
|
|
end
|
| 532 |
|
|
3'b001 : begin
|
| 533 |
|
|
// C.JAL
|
| 534 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
|
| 535 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
|
| 536 |
|
|
idu2exu_cmd_o.jump_req = 1'b1;
|
| 537 |
|
|
idu2exu_cmd_o.rd_addr = SCR1_MPRF_RA_ADDR;
|
| 538 |
|
|
idu2exu_cmd_o.imm = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
|
| 539 |
|
|
end
|
| 540 |
|
|
3'b010 : begin
|
| 541 |
|
|
// C.LI
|
| 542 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IMM;
|
| 543 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 544 |
|
|
idu2exu_cmd_o.imm = {{27{instr[12]}}, instr[6:2]};
|
| 545 |
|
|
`ifdef SCR1_RVE_EXT
|
| 546 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 547 |
|
|
`endif // SCR1_RVE_EXT
|
| 548 |
|
|
end
|
| 549 |
|
|
3'b011 : begin
|
| 550 |
|
|
if (~|{instr[12], instr[6:2]}) rvc_illegal = 1'b1;
|
| 551 |
|
|
if (instr[11:7] == SCR1_MPRF_SP_ADDR) begin
|
| 552 |
|
|
// C.ADDI16SP
|
| 553 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 554 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
|
| 555 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 556 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 557 |
|
|
idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
|
| 558 |
|
|
idu2exu_cmd_o.rd_addr = SCR1_MPRF_SP_ADDR;
|
| 559 |
|
|
idu2exu_cmd_o.imm = {{23{instr[12]}}, instr[4:3], instr[5], instr[2], instr[6], 4'd0};
|
| 560 |
|
|
end else begin
|
| 561 |
|
|
// C.LUI
|
| 562 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IMM;
|
| 563 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 564 |
|
|
idu2exu_cmd_o.imm = {{15{instr[12]}}, instr[6:2], 12'd0};
|
| 565 |
|
|
`ifdef SCR1_RVE_EXT
|
| 566 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 567 |
|
|
`endif // SCR1_RVE_EXT
|
| 568 |
|
|
end
|
| 569 |
|
|
end
|
| 570 |
|
|
3'b100 : begin
|
| 571 |
|
|
idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
|
| 572 |
|
|
idu2exu_cmd_o.rd_addr = {2'b01, instr[9:7]};
|
| 573 |
|
|
idu2exu_cmd_o.rs2_addr = {2'b01, instr[4:2]};
|
| 574 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 575 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 576 |
|
|
case (instr[11:10])
|
| 577 |
|
|
2'b00 : begin
|
| 578 |
|
|
if (instr[12]) rvc_illegal = 1'b1;
|
| 579 |
|
|
// C.SRLI
|
| 580 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 581 |
|
|
idu2exu_cmd_o.imm = {27'd0, instr[6:2]};
|
| 582 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRL;
|
| 583 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 584 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 585 |
|
|
end
|
| 586 |
|
|
2'b01 : begin
|
| 587 |
|
|
if (instr[12]) rvc_illegal = 1'b1;
|
| 588 |
|
|
// C.SRAI
|
| 589 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 590 |
|
|
idu2exu_cmd_o.imm = {27'd0, instr[6:2]};
|
| 591 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SRA;
|
| 592 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 593 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 594 |
|
|
end
|
| 595 |
|
|
2'b10 : begin
|
| 596 |
|
|
// C.ANDI
|
| 597 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 598 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND;
|
| 599 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 600 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 601 |
|
|
idu2exu_cmd_o.imm = {{27{instr[12]}}, instr[6:2]};
|
| 602 |
|
|
end
|
| 603 |
|
|
2'b11 : begin
|
| 604 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 605 |
|
|
case ({instr[12], instr[6:5]})
|
| 606 |
|
|
3'b000 : begin
|
| 607 |
|
|
// C.SUB
|
| 608 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB;
|
| 609 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 610 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 611 |
|
|
end
|
| 612 |
|
|
3'b001 : begin
|
| 613 |
|
|
// C.XOR
|
| 614 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_XOR;
|
| 615 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 616 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 617 |
|
|
end
|
| 618 |
|
|
3'b010 : begin
|
| 619 |
|
|
// C.OR
|
| 620 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_OR;
|
| 621 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 622 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 623 |
|
|
end
|
| 624 |
|
|
3'b011 : begin
|
| 625 |
|
|
// C.AND
|
| 626 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_AND;
|
| 627 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 628 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 629 |
|
|
end
|
| 630 |
|
|
default : begin
|
| 631 |
|
|
rvc_illegal = 1'b1;
|
| 632 |
|
|
end
|
| 633 |
|
|
endcase // {instr[12], instr[6:5]}
|
| 634 |
|
|
end
|
| 635 |
|
|
endcase // instr[11:10]
|
| 636 |
|
|
end // funct3 == 3'b100
|
| 637 |
|
|
3'b101 : begin
|
| 638 |
|
|
// C.J
|
| 639 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 640 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
|
| 641 |
|
|
idu2exu_cmd_o.jump_req = 1'b1;
|
| 642 |
|
|
idu2exu_cmd_o.imm = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
|
| 643 |
|
|
end
|
| 644 |
|
|
3'b110 : begin
|
| 645 |
|
|
// C.BEQZ
|
| 646 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 647 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 648 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 649 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_EQ;
|
| 650 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 651 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
|
| 652 |
|
|
idu2exu_cmd_o.branch_req = 1'b1;
|
| 653 |
|
|
idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
|
| 654 |
|
|
idu2exu_cmd_o.rs2_addr = SCR1_MPRF_ZERO_ADDR;
|
| 655 |
|
|
idu2exu_cmd_o.imm = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
|
| 656 |
|
|
end
|
| 657 |
|
|
3'b111 : begin
|
| 658 |
|
|
// C.BNEZ
|
| 659 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 660 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 661 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 662 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SUB_NE;
|
| 663 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 664 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_PC_IMM;
|
| 665 |
|
|
idu2exu_cmd_o.branch_req = 1'b1;
|
| 666 |
|
|
idu2exu_cmd_o.rs1_addr = {2'b01, instr[9:7]};
|
| 667 |
|
|
idu2exu_cmd_o.rs2_addr = SCR1_MPRF_ZERO_ADDR;
|
| 668 |
|
|
idu2exu_cmd_o.imm = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
|
| 669 |
|
|
end
|
| 670 |
|
|
endcase // funct3
|
| 671 |
|
|
end // Quadrant 1
|
| 672 |
|
|
|
| 673 |
|
|
// Quadrant 2
|
| 674 |
|
|
SCR1_INSTR_RVC2 : begin
|
| 675 |
|
|
idu2exu_cmd_o.instr_rvc = 1'b1;
|
| 676 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 677 |
|
|
case (funct3)
|
| 678 |
|
|
3'b000 : begin
|
| 679 |
|
|
if (instr[12]) rvc_illegal = 1'b1;
|
| 680 |
|
|
// C.SLLI
|
| 681 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 682 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 683 |
|
|
idu2exu_cmd_o.rs1_addr = instr[11:7];
|
| 684 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 685 |
|
|
idu2exu_cmd_o.imm = {27'd0, instr[6:2]};
|
| 686 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_SLL;
|
| 687 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_IMM;
|
| 688 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 689 |
|
|
`ifdef SCR1_RVE_EXT
|
| 690 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 691 |
|
|
`endif // SCR1_RVE_EXT
|
| 692 |
|
|
end
|
| 693 |
|
|
3'b010 : begin
|
| 694 |
|
|
if (~|instr[11:7]) rvc_illegal = 1'b1;
|
| 695 |
|
|
// C.LWSP
|
| 696 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 697 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 698 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 699 |
|
|
idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_LW;
|
| 700 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_LSU;
|
| 701 |
|
|
idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
|
| 702 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 703 |
|
|
idu2exu_cmd_o.imm = {24'd0, instr[3:2], instr[12], instr[6:4], 2'b00};
|
| 704 |
|
|
`ifdef SCR1_RVE_EXT
|
| 705 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 706 |
|
|
`endif // SCR1_RVE_EXT
|
| 707 |
|
|
end
|
| 708 |
|
|
3'b100 : begin
|
| 709 |
|
|
if (~instr[12]) begin
|
| 710 |
|
|
if (|instr[6:2]) begin
|
| 711 |
|
|
// C.MV
|
| 712 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 713 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 714 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
|
| 715 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 716 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 717 |
|
|
idu2exu_cmd_o.rs1_addr = SCR1_MPRF_ZERO_ADDR;
|
| 718 |
|
|
idu2exu_cmd_o.rs2_addr = instr[6:2];
|
| 719 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 720 |
|
|
`ifdef SCR1_RVE_EXT
|
| 721 |
|
|
if (instr[11]|instr[6]) rve_illegal = 1'b1;
|
| 722 |
|
|
`endif // SCR1_RVE_EXT
|
| 723 |
|
|
end else begin
|
| 724 |
|
|
if (~|instr[11:7]) rvc_illegal = 1'b1;
|
| 725 |
|
|
// C.JR
|
| 726 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 727 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 728 |
|
|
idu2exu_cmd_o.jump_req = 1'b1;
|
| 729 |
|
|
idu2exu_cmd_o.rs1_addr = instr[11:7];
|
| 730 |
|
|
idu2exu_cmd_o.imm = 0;
|
| 731 |
|
|
`ifdef SCR1_RVE_EXT
|
| 732 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 733 |
|
|
`endif // SCR1_RVE_EXT
|
| 734 |
|
|
end
|
| 735 |
|
|
end else begin // instr[12] == 1
|
| 736 |
|
|
if (~|instr[11:2]) begin
|
| 737 |
|
|
// C.EBREAK
|
| 738 |
|
|
idu2exu_cmd_o.exc_req = 1'b1;
|
| 739 |
|
|
idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_BREAKPOINT;
|
| 740 |
|
|
end else if (~|instr[6:2]) begin
|
| 741 |
|
|
// C.JALR
|
| 742 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 743 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 744 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 745 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 746 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_INC_PC;
|
| 747 |
|
|
idu2exu_cmd_o.jump_req = 1'b1;
|
| 748 |
|
|
idu2exu_cmd_o.rs1_addr = instr[11:7];
|
| 749 |
|
|
idu2exu_cmd_o.rd_addr = SCR1_MPRF_RA_ADDR;
|
| 750 |
|
|
idu2exu_cmd_o.imm = 0;
|
| 751 |
|
|
`ifdef SCR1_RVE_EXT
|
| 752 |
|
|
if (instr[11]) rve_illegal = 1'b1;
|
| 753 |
|
|
`endif // SCR1_RVE_EXT
|
| 754 |
|
|
end else begin
|
| 755 |
|
|
// C.ADD
|
| 756 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 757 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 758 |
|
|
idu2exu_use_rd_o = 1'b1;
|
| 759 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_ADD;
|
| 760 |
|
|
idu2exu_cmd_o.ialu_op = SCR1_IALU_OP_REG_REG;
|
| 761 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_IALU;
|
| 762 |
|
|
idu2exu_cmd_o.rs1_addr = instr[11:7];
|
| 763 |
|
|
idu2exu_cmd_o.rs2_addr = instr[6:2];
|
| 764 |
|
|
idu2exu_cmd_o.rd_addr = instr[11:7];
|
| 765 |
|
|
`ifdef SCR1_RVE_EXT
|
| 766 |
|
|
if (instr[11]|instr[6]) rve_illegal = 1'b1;
|
| 767 |
|
|
`endif // SCR1_RVE_EXT
|
| 768 |
|
|
end
|
| 769 |
|
|
end // instr[12] == 1
|
| 770 |
|
|
end
|
| 771 |
|
|
3'b110 : begin
|
| 772 |
|
|
// C.SWSP
|
| 773 |
|
|
idu2exu_use_rs1_o = 1'b1;
|
| 774 |
|
|
idu2exu_use_rs2_o = 1'b1;
|
| 775 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 776 |
|
|
idu2exu_cmd_o.sum2_op = SCR1_SUM2_OP_REG_IMM;
|
| 777 |
|
|
idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_SW;
|
| 778 |
|
|
idu2exu_cmd_o.rs1_addr = SCR1_MPRF_SP_ADDR;
|
| 779 |
|
|
idu2exu_cmd_o.rs2_addr = instr[6:2];
|
| 780 |
|
|
idu2exu_cmd_o.imm = {24'd0, instr[8:7], instr[12:9], 2'b00};
|
| 781 |
|
|
`ifdef SCR1_RVE_EXT
|
| 782 |
|
|
if (instr[6]) rve_illegal = 1'b1;
|
| 783 |
|
|
`endif // SCR1_RVE_EXT
|
| 784 |
|
|
end
|
| 785 |
|
|
default : begin
|
| 786 |
|
|
rvc_illegal = 1'b1;
|
| 787 |
|
|
end
|
| 788 |
|
|
endcase // funct3
|
| 789 |
|
|
end // Quadrant 2
|
| 790 |
|
|
|
| 791 |
|
|
default : begin
|
| 792 |
|
|
end
|
| 793 |
|
|
`else // SCR1_RVC_EXT
|
| 794 |
|
|
default : begin
|
| 795 |
|
|
idu2exu_cmd_o.instr_rvc = 1'b1;
|
| 796 |
|
|
rvi_illegal = 1'b1;
|
| 797 |
|
|
end
|
| 798 |
|
|
`endif // SCR1_RVC_EXT
|
| 799 |
|
|
endcase // instr_type
|
| 800 |
|
|
end // no imem fault
|
| 801 |
|
|
|
| 802 |
|
|
// At this point the instruction is fully decoded
|
| 803 |
|
|
// given that no imem fault has happened
|
| 804 |
|
|
|
| 805 |
|
|
// Check illegal instruction
|
| 806 |
|
|
if (
|
| 807 |
|
|
rvi_illegal
|
| 808 |
|
|
`ifdef SCR1_RVC_EXT
|
| 809 |
|
|
| rvc_illegal
|
| 810 |
|
|
`endif
|
| 811 |
|
|
`ifdef SCR1_RVE_EXT
|
| 812 |
|
|
| rve_illegal
|
| 813 |
|
|
`endif
|
| 814 |
|
|
) begin
|
| 815 |
|
|
idu2exu_cmd_o.ialu_cmd = SCR1_IALU_CMD_NONE;
|
| 816 |
|
|
idu2exu_cmd_o.lsu_cmd = SCR1_LSU_CMD_NONE;
|
| 817 |
|
|
idu2exu_cmd_o.csr_cmd = SCR1_CSR_CMD_NONE;
|
| 818 |
|
|
idu2exu_cmd_o.rd_wb_sel = SCR1_RD_WB_NONE;
|
| 819 |
|
|
idu2exu_cmd_o.jump_req = 1'b0;
|
| 820 |
|
|
idu2exu_cmd_o.branch_req = 1'b0;
|
| 821 |
|
|
idu2exu_cmd_o.mret_req = 1'b0;
|
| 822 |
|
|
idu2exu_cmd_o.fencei_req = 1'b0;
|
| 823 |
|
|
idu2exu_cmd_o.wfi_req = 1'b0;
|
| 824 |
|
|
|
| 825 |
|
|
idu2exu_use_rs1_o = 1'b0;
|
| 826 |
|
|
idu2exu_use_rs2_o = 1'b0;
|
| 827 |
|
|
idu2exu_use_rd_o = 1'b0;
|
| 828 |
|
|
|
| 829 |
|
|
`ifndef SCR1_MTVAL_ILLEGAL_INSTR_EN
|
| 830 |
|
|
idu2exu_use_imm_o = 1'b0;
|
| 831 |
|
|
`else // SCR1_MTVAL_ILLEGAL_INSTR_EN
|
| 832 |
|
|
idu2exu_use_imm_o = 1'b1;
|
| 833 |
|
|
idu2exu_cmd_o.imm = instr;
|
| 834 |
|
|
`endif // SCR1_MTVAL_ILLEGAL_INSTR_EN
|
| 835 |
|
|
|
| 836 |
|
|
idu2exu_cmd_o.exc_req = 1'b1;
|
| 837 |
|
|
idu2exu_cmd_o.exc_code = SCR1_EXC_CODE_ILLEGAL_INSTR;
|
| 838 |
|
|
end
|
| 839 |
|
|
|
| 840 |
|
|
end // RV32I(MC) decode
|
| 841 |
|
|
|
| 842 |
|
|
`ifdef SCR1_TRGT_SIMULATION
|
| 843 |
|
|
//-------------------------------------------------------------------------------
|
| 844 |
|
|
// Assertion
|
| 845 |
|
|
//-------------------------------------------------------------------------------
|
| 846 |
|
|
|
| 847 |
|
|
// X checks
|
| 848 |
|
|
|
| 849 |
|
|
SCR1_SVA_IDU_XCHECK : assert property (
|
| 850 |
|
|
@(negedge clk) disable iff (~rst_n)
|
| 851 |
|
|
!$isunknown({ifu2idu_vd_i, exu2idu_rdy_i})
|
| 852 |
|
|
) else $error("IDU Error: unknown values");
|
| 853 |
|
|
|
| 854 |
|
|
SCR1_SVA_IDU_XCHECK2 : assert property (
|
| 855 |
|
|
@(negedge clk) disable iff (~rst_n)
|
| 856 |
|
|
ifu2idu_vd_i |-> !$isunknown({ifu2idu_imem_err_i, (ifu2idu_imem_err_i ? 0 : ifu2idu_instr_i)})
|
| 857 |
|
|
) else $error("IDU Error: unknown values");
|
| 858 |
|
|
|
| 859 |
|
|
// Behavior checks
|
| 860 |
|
|
|
| 861 |
|
|
SCR1_SVA_IDU_IALU_CMD_RANGE : assert property (
|
| 862 |
|
|
@(negedge clk) disable iff (~rst_n)
|
| 863 |
|
|
(ifu2idu_vd_i & ~ifu2idu_imem_err_i) |->
|
| 864 |
|
|
((idu2exu_cmd_o.ialu_cmd >= SCR1_IALU_CMD_NONE) &
|
| 865 |
|
|
(idu2exu_cmd_o.ialu_cmd <=
|
| 866 |
|
|
`ifdef SCR1_RVM_EXT
|
| 867 |
|
|
SCR1_IALU_CMD_REMU
|
| 868 |
|
|
`else
|
| 869 |
|
|
SCR1_IALU_CMD_SRA
|
| 870 |
|
|
`endif // SCR1_RVM_EXT
|
| 871 |
|
|
))
|
| 872 |
|
|
) else $error("IDU Error: IALU_CMD out of range");
|
| 873 |
|
|
|
| 874 |
|
|
`endif // SCR1_TRGT_SIMULATION
|
| 875 |
|
|
|
| 876 |
|
|
endmodule : scr1_pipe_idu
|
