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dinesha |
/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details
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/// @file
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/// @brief SCR1 pipeline top
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///
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`include "scr1_arch_description.svh"
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`include "scr1_memif.svh"
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`include "scr1_riscv_isa_decoding.svh"
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`include "scr1_csr.svh"
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`ifdef SCR1_IPIC_EN
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`include "scr1_ipic.svh"
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_DBG_EN
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`include "scr1_hdu.svh"
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`endif // SCR1_DBG_EN
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`ifdef SCR1_TDU_EN
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`include "scr1_tdu.svh"
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`endif // SCR1_TDU_EN
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module scr1_pipe_top (
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// Common
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input logic pipe_rst_n, // Pipe reset
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`ifdef SCR1_DBG_EN
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input logic pipe2hdu_rdc_qlfy_i, // Pipe RDC qualifier
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input logic dbg_rst_n, // Debug reset
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`endif // SCR1_DBG_EN
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input logic clk, // Pipe clock
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// Instruction Memory Interface
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output logic pipe2imem_req_o, // IMEM request
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output type_scr1_mem_cmd_e pipe2imem_cmd_o, // IMEM command
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output logic [`SCR1_IMEM_AWIDTH-1:0] pipe2imem_addr_o, // IMEM address
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input logic imem2pipe_req_ack_i, // IMEM request acknowledge
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input logic [`SCR1_IMEM_DWIDTH-1:0] imem2pipe_rdata_i, // IMEM read data
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input type_scr1_mem_resp_e imem2pipe_resp_i, // IMEM response
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// Data Memory Interface
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output logic pipe2dmem_req_o, // DMEM request
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output type_scr1_mem_cmd_e pipe2dmem_cmd_o, // DMEM command
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output type_scr1_mem_width_e pipe2dmem_width_o, // DMEM data width
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output logic [`SCR1_DMEM_AWIDTH-1:0] pipe2dmem_addr_o, // DMEM address
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output logic [`SCR1_DMEM_DWIDTH-1:0] pipe2dmem_wdata_o, // DMEM write data
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input logic dmem2pipe_req_ack_i, // DMEM request acknowledge
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input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2pipe_rdata_i, // DMEM read data
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input type_scr1_mem_resp_e dmem2pipe_resp_i, // DMEM response
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`ifdef SCR1_DBG_EN
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// Debug interface:
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input logic dbg_en, // 1 - debug operations enabled
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// DM <-> Pipeline: HART Run Control i/f
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input logic dm2pipe_active_i, // Debug Module active flag
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input logic dm2pipe_cmd_req_i, // Request from Debug Module
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input type_scr1_hdu_dbgstates_e dm2pipe_cmd_i, // Command from Debug Module
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output logic pipe2dm_cmd_resp_o, // Response to Debug Module
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output logic pipe2dm_cmd_rcode_o, // Debug Module return code: 0 - Ok; 1 - Error
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output logic pipe2dm_hart_event_o, // HART event flag
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output type_scr1_hdu_hartstatus_s pipe2dm_hart_status_o, // HART status
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// DM <-> Pipeline: Program Buffer - HART instruction execution i/f
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output logic [SCR1_HDU_PBUF_ADDR_WIDTH-1:0] pipe2dm_pbuf_addr_o, // Program Buffer address
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input logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] dm2pipe_pbuf_instr_i, // Program Buffer instruction
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// DM <-> Pipeline: HART Abstract Data regs i/f
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output logic pipe2dm_dreg_req_o, // Abstract Data Register request
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output logic pipe2dm_dreg_wr_o, // Abstract Data Register write
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output logic [`SCR1_XLEN-1:0] pipe2dm_dreg_wdata_o, // Abstract Data Register write data
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input logic dm2pipe_dreg_resp_i, // Abstract Data Register response
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input logic dm2pipe_dreg_fail_i, // Abstract Data Register fail - possibly not needed?
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input logic [`SCR1_XLEN-1:0] dm2pipe_dreg_rdata_i, // Abstract Data Register read data
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// DM <-> Pipeling: PC i/f
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output logic [`SCR1_XLEN-1:0] pipe2dm_pc_sample_o, // Current PC for sampling
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`endif // SCR1_DBG_EN
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// IRQ
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`ifdef SCR1_IPIC_EN
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input logic [SCR1_IRQ_LINES_NUM-1:0] soc2pipe_irq_lines_i, // External interrupt request lines
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`else // SCR1_IPIC_EN
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input logic soc2pipe_irq_ext_i, // External interrupt request
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`endif // SCR1_IPIC_EN
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input logic soc2pipe_irq_soft_i, // Software generated interrupt request
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input logic soc2pipe_irq_mtimer_i, // Machine timer interrupt request
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// Memory-mapped external timer
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input logic [63:0] soc2pipe_mtimer_val_i, // Machine timer value
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`ifdef SCR1_CLKCTRL_EN
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// CLK_CTRL interface
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output logic pipe2clkctl_sleep_req_o, // CLK disable request to CLK gating circuit
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output logic pipe2clkctl_wake_req_o, // CLK enable request to CLK gating circuit
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input logic clkctl2pipe_clk_alw_on_i, // Not gated CLK
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input logic clkctl2pipe_clk_dbgc_i, // CLK for HDU (not gated for now)
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input logic clkctl2pipe_clk_en_i, // CLK enabled flag
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`endif // SCR1_CLKCTRL_EN
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// Fuse
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input logic [`SCR1_XLEN-1:0] soc2pipe_fuse_mhartid_i // Fuse MHARTID value
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);
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//-------------------------------------------------------------------------------
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// Local signals declaration
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//-------------------------------------------------------------------------------
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// Pipeline control
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logic [`SCR1_XLEN-1:0] curr_pc; // Current PC
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logic [`SCR1_XLEN-1:0] next_pc; // Is written to MEPC on interrupt trap
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logic new_pc_req; // New PC request (jumps, branches, traps etc)
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logic [`SCR1_XLEN-1:0] new_pc; // New PC
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logic stop_fetch; // Stop IFU
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logic exu_exc_req; // Exception request
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logic brkpt; // Breakpoint (sw) on current instruction
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logic exu_init_pc; // Reset exit
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logic wfi_run2halt; // Transition to WFI halted state
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logic instret; // Instruction retirement (with or without exception)
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logic instret_nexc; // Instruction retirement (without exception)
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`ifdef SCR1_IPIC_EN
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logic ipic2csr_irq; // IRQ request from IPIC
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_TDU_EN
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logic brkpt_hw; // Hardware breakpoint on current instruction
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`endif // SCR1_TDU_EN
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`ifdef SCR1_CLKCTRL_EN
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logic imem_txns_pending; // There are pending imem transactions
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logic wfi_halted; // WFI halted state
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`endif // SCR1_CLKCTRL_EN
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// IFU <-> IDU
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logic ifu2idu_vd; // IFU request
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logic [`SCR1_IMEM_DWIDTH-1:0] ifu2idu_instr; // IFU instruction
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logic ifu2idu_imem_err; // IFU instruction access fault
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logic ifu2idu_err_rvi_hi; // 1 - imem fault when trying to fetch second half of an unaligned RVI instruction
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logic idu2ifu_rdy; // IDU ready for new data
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// IDU <-> EXU
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logic idu2exu_req; // IDU request
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type_scr1_exu_cmd_s idu2exu_cmd; // IDU command (see scr1_riscv_isa_decoding.svh)
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logic idu2exu_use_rs1; // Instruction uses rs1
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logic idu2exu_use_rs2; // Instruction uses rs2
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logic idu2exu_use_rd; // Instruction uses rd
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logic idu2exu_use_imm; // Instruction uses immediate
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logic exu2idu_rdy; // EXU ready for new data
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// EXU <-> MPRF
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logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs1_addr; // MPRF rs1 read address
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logic [`SCR1_XLEN-1:0] mprf2exu_rs1_data; // MPRF rs1 read data
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logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rs2_addr; // MPRF rs2 read address
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logic [`SCR1_XLEN-1:0] mprf2exu_rs2_data; // MPRF rs2 read data
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logic exu2mprf_w_req; // MPRF write request
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logic [`SCR1_MPRF_AWIDTH-1:0] exu2mprf_rd_addr; // MPRF rd write address
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logic [`SCR1_XLEN-1:0] exu2mprf_rd_data; // MPRF rd write data
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// EXU <-> CSR
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logic [SCR1_CSR_ADDR_WIDTH-1:0] exu2csr_rw_addr; // CSR read/write address
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logic exu2csr_r_req; // CSR read request
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logic [`SCR1_XLEN-1:0] csr2exu_r_data; // CSR read data
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logic exu2csr_w_req; // CSR write request
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type_scr1_csr_cmd_sel_e exu2csr_w_cmd; // CSR write command
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logic [`SCR1_XLEN-1:0] exu2csr_w_data; // CSR write data
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logic csr2exu_rw_exc; // CSR read/write access exception
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// EXU <-> CSR event interface
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logic exu2csr_take_irq; // Take IRQ trap
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logic exu2csr_take_exc; // Take exception trap
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logic exu2csr_mret_update; // MRET update CSR
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logic exu2csr_mret_instr; // MRET instruction
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type_scr1_exc_code_e exu2csr_exc_code; // Exception code (see scr1_arch_types.svh)
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logic [`SCR1_XLEN-1:0] exu2csr_trap_val; // Trap value
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logic [`SCR1_XLEN-1:0] csr2exu_new_pc; // Exception/IRQ/MRET new PC
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logic csr2exu_irq; // IRQ request
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logic csr2exu_ip_ie; // Some IRQ pending and locally enabled
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logic csr2exu_mstatus_mie_up; // MSTATUS or MIE update in the current cycle
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`ifdef SCR1_IPIC_EN
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// CSR <-> IPIC
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logic csr2ipic_r_req; // IPIC read request
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logic csr2ipic_w_req; // IPIC write request
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logic [2:0] csr2ipic_addr; // IPIC address
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logic [`SCR1_XLEN-1:0] csr2ipic_wdata; // IPIC write data
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logic [`SCR1_XLEN-1:0] ipic2csr_rdata; // IPIC read data
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`endif // SCR1_IPIC_EN
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`ifdef SCR1_TDU_EN
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// CSR <-> TDU
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logic csr2tdu_req; // Request to TDU
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type_scr1_csr_cmd_sel_e csr2tdu_cmd; // TDU command
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logic [SCR1_CSR_ADDR_TDU_OFFS_W-1:0] csr2tdu_addr; // TDU address
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logic [`SCR1_XLEN-1:0] csr2tdu_wdata; // TDU write data
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logic [`SCR1_XLEN-1:0] tdu2csr_rdata; // TDU read data
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type_scr1_csr_resp_e tdu2csr_resp; // TDU response
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`ifdef SCR1_DBG_EN
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// Qualified TDU input signals from pipe_rst_n
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// reset domain:
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logic csr2tdu_req_qlfy; // Request to TDU
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`endif // SCR1_DBG_EN
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// EXU/LSU <-> TDU
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type_scr1_brkm_instr_mon_s exu2tdu_i_mon; // Instruction monitor
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type_scr1_brkm_lsu_mon_s lsu2tdu_d_mon; // Data monitor
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logic [SCR1_TDU_ALLTRIG_NUM-1:0] tdu2exu_i_match; // Instruction breakpoint(s) match
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logic [SCR1_TDU_MTRIG_NUM-1:0] tdu2lsu_d_match; // Data breakpoint(s) match
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logic tdu2exu_i_x_req; // Instruction breakpoint exception
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logic tdu2lsu_i_x_req; // Instruction breakpoint exception
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logic tdu2lsu_d_x_req; // Data breakpoint exception
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logic [SCR1_TDU_ALLTRIG_NUM-1:0] exu2tdu_bp_retire; // Instruction with breakpoint flag retire
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`ifdef SCR1_DBG_EN
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// Qualified TDU input signals from pipe_rst_n
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// reset domain:
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type_scr1_brkm_instr_mon_s exu2tdu_i_mon_qlfy; // Instruction monitor
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type_scr1_brkm_lsu_mon_s lsu2tdu_d_mon_qlfy; // Data monitor
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logic [SCR1_TDU_ALLTRIG_NUM-1:0] exu2tdu_bp_retire_qlfy; // Instruction with breakpoint flag retire
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`endif // SCR1_DBG_EN
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`endif // SCR1_TDU_EN
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`ifdef SCR1_DBG_EN
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// Debug signals:
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logic fetch_pbuf; // Fetch instructions provided by Program Buffer (via HDU)
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logic csr2hdu_req; // Request to HDU
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type_scr1_csr_cmd_sel_e csr2hdu_cmd; // HDU command
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logic [SCR1_HDU_DEBUGCSR_ADDR_WIDTH-1:0] csr2hdu_addr; // HDU address
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logic [`SCR1_XLEN-1:0] csr2hdu_wdata; // HDU write data
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logic [`SCR1_XLEN-1:0] hdu2csr_rdata; // HDU read data
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type_scr1_csr_resp_e hdu2csr_resp; // HDU response
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// Qualified HDU input signals from pipe_rst_n
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// reset domain:
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logic csr2hdu_req_qlfy; // Request to HDU
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logic hwbrk_dsbl; // Disables TDU
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logic hdu_hwbrk_dsbl; // Disables TDU
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logic tdu2hdu_dmode_req; // TDU requests transition to debug mode
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logic exu_no_commit; // Forbid instruction commitment
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logic exu_irq_dsbl; // Disable IRQ
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logic exu_pc_advmt_dsbl; // Forbid PC advancement
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logic exu_dmode_sstep_en; // Enable single-step
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logic dbg_halted; // Debug halted state
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logic dbg_run2halt; // Transition to debug halted state
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logic dbg_halt2run; // Transition to run state
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logic dbg_run_start; // First cycle of run state
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logic [`SCR1_XLEN-1:0] dbg_new_pc; // New PC as starting point for HART Resume
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logic ifu2hdu_pbuf_rdy;
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logic hdu2ifu_pbuf_vd;
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logic hdu2ifu_pbuf_err;
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logic [SCR1_HDU_CORE_INSTR_WIDTH-1:0] hdu2ifu_pbuf_instr;
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// Qualified HDU input signals from pipe_rst_n reset domain:
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logic ifu2hdu_pbuf_rdy_qlfy;
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logic exu_busy_qlfy;
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logic instret_qlfy;
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logic exu_init_pc_qlfy;
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logic exu_exc_req_qlfy;
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logic brkpt_qlfy;
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`endif // SCR1_DBG_EN
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logic exu_busy;
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`ifndef SCR1_CLKCTRL_EN
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logic pipe2clkctl_wake_req_o;
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`endif // SCR1_CLKCTRL_EN
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//-------------------------------------------------------------------------------
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// Pipeline logic
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| 270 |
|
|
//-------------------------------------------------------------------------------
|
| 271 |
|
|
assign stop_fetch = wfi_run2halt
|
| 272 |
|
|
`ifdef SCR1_DBG_EN
|
| 273 |
|
|
| fetch_pbuf
|
| 274 |
|
|
`endif // SCR1_DBG_EN
|
| 275 |
|
|
;
|
| 276 |
|
|
|
| 277 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 278 |
|
|
assign pipe2clkctl_sleep_req_o = wfi_halted & ~imem_txns_pending;
|
| 279 |
|
|
assign pipe2clkctl_wake_req_o = csr2exu_ip_ie
|
| 280 |
|
|
`ifdef SCR1_DBG_EN
|
| 281 |
|
|
| dm2pipe_active_i
|
| 282 |
|
|
`endif // SCR1_DBG_EN
|
| 283 |
|
|
;
|
| 284 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 285 |
|
|
|
| 286 |
|
|
`ifdef SCR1_DBG_EN
|
| 287 |
|
|
assign pipe2dm_pc_sample_o = curr_pc;
|
| 288 |
|
|
`endif // SCR1_DBG_EN
|
| 289 |
|
|
|
| 290 |
|
|
//-------------------------------------------------------------------------------
|
| 291 |
|
|
// Instruction fetch unit
|
| 292 |
|
|
//-------------------------------------------------------------------------------
|
| 293 |
|
|
scr1_pipe_ifu i_pipe_ifu (
|
| 294 |
|
|
.rst_n (pipe_rst_n ),
|
| 295 |
|
|
.clk (clk ),
|
| 296 |
|
|
|
| 297 |
|
|
// Instruction memory interface
|
| 298 |
|
|
.imem2ifu_req_ack_i (imem2pipe_req_ack_i),
|
| 299 |
|
|
.ifu2imem_req_o (pipe2imem_req_o ),
|
| 300 |
|
|
.ifu2imem_cmd_o (pipe2imem_cmd_o ),
|
| 301 |
|
|
.ifu2imem_addr_o (pipe2imem_addr_o ),
|
| 302 |
|
|
.imem2ifu_rdata_i (imem2pipe_rdata_i ),
|
| 303 |
|
|
.imem2ifu_resp_i (imem2pipe_resp_i ),
|
| 304 |
|
|
|
| 305 |
|
|
// New PC interface
|
| 306 |
|
|
.exu2ifu_pc_new_req_i (new_pc_req ),
|
| 307 |
|
|
.exu2ifu_pc_new_i (new_pc ),
|
| 308 |
|
|
.pipe2ifu_stop_fetch_i (stop_fetch ),
|
| 309 |
|
|
|
| 310 |
|
|
`ifdef SCR1_DBG_EN
|
| 311 |
|
|
// IFU <-> HDU Program Buffer interface
|
| 312 |
|
|
.hdu2ifu_pbuf_fetch_i (fetch_pbuf ),
|
| 313 |
|
|
.ifu2hdu_pbuf_rdy_o (ifu2hdu_pbuf_rdy ),
|
| 314 |
|
|
.hdu2ifu_pbuf_vd_i (hdu2ifu_pbuf_vd ),
|
| 315 |
|
|
.hdu2ifu_pbuf_err_i (hdu2ifu_pbuf_err ),
|
| 316 |
|
|
.hdu2ifu_pbuf_instr_i (hdu2ifu_pbuf_instr ),
|
| 317 |
|
|
`endif // SCR1_DBG_EN
|
| 318 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 319 |
|
|
.ifu2pipe_imem_txns_pnd_o (imem_txns_pending ),
|
| 320 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 321 |
|
|
|
| 322 |
|
|
// IFU <-> IDU interface
|
| 323 |
|
|
.idu2ifu_rdy_i (idu2ifu_rdy ),
|
| 324 |
|
|
.ifu2idu_instr_o (ifu2idu_instr ),
|
| 325 |
|
|
.ifu2idu_imem_err_o (ifu2idu_imem_err ),
|
| 326 |
|
|
.ifu2idu_err_rvi_hi_o (ifu2idu_err_rvi_hi ),
|
| 327 |
|
|
.ifu2idu_vd_o (ifu2idu_vd )
|
| 328 |
|
|
);
|
| 329 |
|
|
|
| 330 |
|
|
//-------------------------------------------------------------------------------
|
| 331 |
|
|
// Instruction decode unit
|
| 332 |
|
|
//-------------------------------------------------------------------------------
|
| 333 |
|
|
scr1_pipe_idu i_pipe_idu (
|
| 334 |
|
|
`ifdef SCR1_TRGT_SIMULATION
|
| 335 |
|
|
.rst_n (pipe_rst_n ),
|
| 336 |
|
|
.clk (clk ),
|
| 337 |
|
|
`endif // SCR1_TRGT_SIMULATION
|
| 338 |
|
|
.idu2ifu_rdy_o (idu2ifu_rdy ),
|
| 339 |
|
|
.ifu2idu_instr_i (ifu2idu_instr ),
|
| 340 |
|
|
.ifu2idu_imem_err_i (ifu2idu_imem_err ),
|
| 341 |
|
|
.ifu2idu_err_rvi_hi_i (ifu2idu_err_rvi_hi),
|
| 342 |
|
|
.ifu2idu_vd_i (ifu2idu_vd ),
|
| 343 |
|
|
|
| 344 |
|
|
.idu2exu_req_o (idu2exu_req ),
|
| 345 |
|
|
.idu2exu_cmd_o (idu2exu_cmd ),
|
| 346 |
|
|
.idu2exu_use_rs1_o (idu2exu_use_rs1 ),
|
| 347 |
|
|
.idu2exu_use_rs2_o (idu2exu_use_rs2 ),
|
| 348 |
|
|
.idu2exu_use_rd_o (idu2exu_use_rd ),
|
| 349 |
|
|
.idu2exu_use_imm_o (idu2exu_use_imm ),
|
| 350 |
|
|
.exu2idu_rdy_i (exu2idu_rdy )
|
| 351 |
|
|
);
|
| 352 |
|
|
|
| 353 |
|
|
//-------------------------------------------------------------------------------
|
| 354 |
|
|
// Execution unit
|
| 355 |
|
|
//-------------------------------------------------------------------------------
|
| 356 |
|
|
scr1_pipe_exu i_pipe_exu (
|
| 357 |
|
|
.rst_n (pipe_rst_n ),
|
| 358 |
|
|
.clk (clk ),
|
| 359 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 360 |
|
|
.clk_alw_on (clkctl2pipe_clk_alw_on_i),
|
| 361 |
|
|
.clk_pipe_en (clkctl2pipe_clk_en_i),
|
| 362 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 363 |
|
|
|
| 364 |
|
|
// IDU <-> EXU interface
|
| 365 |
|
|
.idu2exu_req_i (idu2exu_req ),
|
| 366 |
|
|
.exu2idu_rdy_o (exu2idu_rdy ),
|
| 367 |
|
|
.idu2exu_cmd_i (idu2exu_cmd ),
|
| 368 |
|
|
.idu2exu_use_rs1_i (idu2exu_use_rs1 ),
|
| 369 |
|
|
.idu2exu_use_rs2_i (idu2exu_use_rs2 ),
|
| 370 |
|
|
`ifndef SCR1_NO_EXE_STAGE
|
| 371 |
|
|
.idu2exu_use_rd_i (idu2exu_use_rd ),
|
| 372 |
|
|
.idu2exu_use_imm_i (idu2exu_use_imm ),
|
| 373 |
|
|
`endif // SCR1_NO_EXE_STAGE
|
| 374 |
|
|
|
| 375 |
|
|
// EXU <-> MPRF interface
|
| 376 |
|
|
.exu2mprf_rs1_addr_o (exu2mprf_rs1_addr ),
|
| 377 |
|
|
.mprf2exu_rs1_data_i (mprf2exu_rs1_data ),
|
| 378 |
|
|
.exu2mprf_rs2_addr_o (exu2mprf_rs2_addr ),
|
| 379 |
|
|
.mprf2exu_rs2_data_i (mprf2exu_rs2_data ),
|
| 380 |
|
|
.exu2mprf_w_req_o (exu2mprf_w_req ),
|
| 381 |
|
|
.exu2mprf_rd_addr_o (exu2mprf_rd_addr ),
|
| 382 |
|
|
.exu2mprf_rd_data_o (exu2mprf_rd_data ),
|
| 383 |
|
|
|
| 384 |
|
|
// EXU <-> CSR read/write interface
|
| 385 |
|
|
.exu2csr_rw_addr_o (exu2csr_rw_addr ),
|
| 386 |
|
|
.exu2csr_r_req_o (exu2csr_r_req ),
|
| 387 |
|
|
.csr2exu_r_data_i (csr2exu_r_data ),
|
| 388 |
|
|
.exu2csr_w_req_o (exu2csr_w_req ),
|
| 389 |
|
|
.exu2csr_w_cmd_o (exu2csr_w_cmd ),
|
| 390 |
|
|
.exu2csr_w_data_o (exu2csr_w_data ),
|
| 391 |
|
|
.csr2exu_rw_exc_i (csr2exu_rw_exc ),
|
| 392 |
|
|
|
| 393 |
|
|
// EXU <-> CSR event interface
|
| 394 |
|
|
.exu2csr_take_irq_o (exu2csr_take_irq ),
|
| 395 |
|
|
.exu2csr_take_exc_o (exu2csr_take_exc ),
|
| 396 |
|
|
.exu2csr_mret_update_o (exu2csr_mret_update ),
|
| 397 |
|
|
.exu2csr_mret_instr_o (exu2csr_mret_instr ),
|
| 398 |
|
|
.exu2csr_exc_code_o (exu2csr_exc_code ),
|
| 399 |
|
|
.exu2csr_trap_val_o (exu2csr_trap_val ),
|
| 400 |
|
|
.csr2exu_new_pc_i (csr2exu_new_pc ),
|
| 401 |
|
|
.csr2exu_irq_i (csr2exu_irq ),
|
| 402 |
|
|
.csr2exu_ip_ie_i (csr2exu_ip_ie ),
|
| 403 |
|
|
.csr2exu_mstatus_mie_up_i (csr2exu_mstatus_mie_up ),
|
| 404 |
|
|
|
| 405 |
|
|
// EXU <-> DMEM interface
|
| 406 |
|
|
.exu2dmem_req_o (pipe2dmem_req_o ),
|
| 407 |
|
|
.exu2dmem_cmd_o (pipe2dmem_cmd_o ),
|
| 408 |
|
|
.exu2dmem_width_o (pipe2dmem_width_o ),
|
| 409 |
|
|
.exu2dmem_addr_o (pipe2dmem_addr_o ),
|
| 410 |
|
|
.exu2dmem_wdata_o (pipe2dmem_wdata_o ),
|
| 411 |
|
|
.dmem2exu_req_ack_i (dmem2pipe_req_ack_i ),
|
| 412 |
|
|
.dmem2exu_rdata_i (dmem2pipe_rdata_i ),
|
| 413 |
|
|
.dmem2exu_resp_i (dmem2pipe_resp_i ),
|
| 414 |
|
|
|
| 415 |
|
|
`ifdef SCR1_DBG_EN
|
| 416 |
|
|
// EXU <-> HDU interface
|
| 417 |
|
|
.hdu2exu_no_commit_i (exu_no_commit ),
|
| 418 |
|
|
.hdu2exu_irq_dsbl_i (exu_irq_dsbl ),
|
| 419 |
|
|
.hdu2exu_pc_advmt_dsbl_i (exu_pc_advmt_dsbl ),
|
| 420 |
|
|
.hdu2exu_dmode_sstep_en_i (exu_dmode_sstep_en ),
|
| 421 |
|
|
.hdu2exu_pbuf_fetch_i (fetch_pbuf ),
|
| 422 |
|
|
.hdu2exu_dbg_halted_i (dbg_halted ),
|
| 423 |
|
|
.hdu2exu_dbg_run2halt_i (dbg_run2halt ),
|
| 424 |
|
|
.hdu2exu_dbg_halt2run_i (dbg_halt2run ),
|
| 425 |
|
|
.hdu2exu_dbg_run_start_i (dbg_run_start ),
|
| 426 |
|
|
.hdu2exu_dbg_new_pc_i (dbg_new_pc ),
|
| 427 |
|
|
`endif // SCR1_DBG_EN
|
| 428 |
|
|
|
| 429 |
|
|
`ifdef SCR1_TDU_EN
|
| 430 |
|
|
// EXU <-> TDU interface
|
| 431 |
|
|
.exu2tdu_imon_o (exu2tdu_i_mon ),
|
| 432 |
|
|
.tdu2exu_ibrkpt_match_i (tdu2exu_i_match ),
|
| 433 |
|
|
.tdu2exu_ibrkpt_exc_req_i (tdu2exu_i_x_req ),
|
| 434 |
|
|
.lsu2tdu_dmon_o (lsu2tdu_d_mon ),
|
| 435 |
|
|
.tdu2lsu_ibrkpt_exc_req_i (tdu2lsu_i_x_req ),
|
| 436 |
|
|
.tdu2lsu_dbrkpt_match_i (tdu2lsu_d_match ),
|
| 437 |
|
|
.tdu2lsu_dbrkpt_exc_req_i (tdu2lsu_d_x_req ),
|
| 438 |
|
|
.exu2tdu_ibrkpt_ret_o (exu2tdu_bp_retire ),
|
| 439 |
|
|
.exu2hdu_ibrkpt_hw_o (brkpt_hw ),
|
| 440 |
|
|
`endif // SCR1_TDU_EN
|
| 441 |
|
|
|
| 442 |
|
|
// EXU control
|
| 443 |
|
|
.exu2pipe_exc_req_o (exu_exc_req ),
|
| 444 |
|
|
.exu2pipe_brkpt_o (brkpt ),
|
| 445 |
|
|
.exu2pipe_init_pc_o (exu_init_pc ),
|
| 446 |
|
|
.exu2pipe_wfi_run2halt_o (wfi_run2halt ),
|
| 447 |
|
|
.exu2pipe_instret_o (instret ),
|
| 448 |
|
|
.exu2csr_instret_no_exc_o (instret_nexc ),
|
| 449 |
|
|
.exu2pipe_exu_busy_o (exu_busy ),
|
| 450 |
|
|
|
| 451 |
|
|
// PC interface
|
| 452 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 453 |
|
|
.exu2pipe_wfi_halted_o (wfi_halted ),
|
| 454 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 455 |
|
|
.exu2pipe_pc_curr_o (curr_pc ),
|
| 456 |
|
|
.exu2csr_pc_next_o (next_pc ),
|
| 457 |
|
|
.exu2ifu_pc_new_req_o (new_pc_req ),
|
| 458 |
|
|
.exu2ifu_pc_new_o (new_pc )
|
| 459 |
|
|
);
|
| 460 |
|
|
|
| 461 |
|
|
//-------------------------------------------------------------------------------
|
| 462 |
|
|
// Multi-port register file
|
| 463 |
|
|
//-------------------------------------------------------------------------------
|
| 464 |
|
|
scr1_pipe_mprf i_pipe_mprf (
|
| 465 |
|
|
`ifdef SCR1_MPRF_RST_EN
|
| 466 |
|
|
.rst_n (pipe_rst_n ),
|
| 467 |
|
|
`endif // SCR1_MPRF_RST_EN
|
| 468 |
|
|
.clk (clk ),
|
| 469 |
|
|
|
| 470 |
|
|
// EXU <-> MPRF interface
|
| 471 |
|
|
.exu2mprf_rs1_addr_i (exu2mprf_rs1_addr),
|
| 472 |
|
|
.mprf2exu_rs1_data_o (mprf2exu_rs1_data),
|
| 473 |
|
|
.exu2mprf_rs2_addr_i (exu2mprf_rs2_addr),
|
| 474 |
|
|
.mprf2exu_rs2_data_o (mprf2exu_rs2_data),
|
| 475 |
|
|
.exu2mprf_w_req_i (exu2mprf_w_req ),
|
| 476 |
|
|
.exu2mprf_rd_addr_i (exu2mprf_rd_addr ),
|
| 477 |
|
|
.exu2mprf_rd_data_i (exu2mprf_rd_data )
|
| 478 |
|
|
);
|
| 479 |
|
|
|
| 480 |
|
|
//-------------------------------------------------------------------------------
|
| 481 |
|
|
// Control and status registers
|
| 482 |
|
|
//-------------------------------------------------------------------------------
|
| 483 |
|
|
scr1_pipe_csr i_pipe_csr (
|
| 484 |
|
|
.rst_n (pipe_rst_n ),
|
| 485 |
|
|
.clk (clk ),
|
| 486 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 487 |
|
|
.clk_alw_on (clkctl2pipe_clk_alw_on_i),
|
| 488 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 489 |
|
|
|
| 490 |
|
|
// EXU <-> CSR read/write interface
|
| 491 |
|
|
.exu2csr_r_req_i (exu2csr_r_req ),
|
| 492 |
|
|
.exu2csr_rw_addr_i (exu2csr_rw_addr ),
|
| 493 |
|
|
.csr2exu_r_data_o (csr2exu_r_data ),
|
| 494 |
|
|
.exu2csr_w_req_i (exu2csr_w_req ),
|
| 495 |
|
|
.exu2csr_w_cmd_i (exu2csr_w_cmd ),
|
| 496 |
|
|
.exu2csr_w_data_i (exu2csr_w_data ),
|
| 497 |
|
|
.csr2exu_rw_exc_o (csr2exu_rw_exc ),
|
| 498 |
|
|
|
| 499 |
|
|
// EXU <-> CSR event interface
|
| 500 |
|
|
.exu2csr_take_irq_i (exu2csr_take_irq ),
|
| 501 |
|
|
.exu2csr_take_exc_i (exu2csr_take_exc ),
|
| 502 |
|
|
.exu2csr_mret_update_i (exu2csr_mret_update ),
|
| 503 |
|
|
.exu2csr_mret_instr_i (exu2csr_mret_instr ),
|
| 504 |
|
|
.exu2csr_exc_code_i (exu2csr_exc_code ),
|
| 505 |
|
|
.exu2csr_trap_val_i (exu2csr_trap_val ),
|
| 506 |
|
|
.csr2exu_new_pc_o (csr2exu_new_pc ),
|
| 507 |
|
|
.csr2exu_irq_o (csr2exu_irq ),
|
| 508 |
|
|
.csr2exu_ip_ie_o (csr2exu_ip_ie ),
|
| 509 |
|
|
.csr2exu_mstatus_mie_up_o (csr2exu_mstatus_mie_up ),
|
| 510 |
|
|
|
| 511 |
|
|
`ifdef SCR1_IPIC_EN
|
| 512 |
|
|
// CSR <-> IPIC interface
|
| 513 |
|
|
.csr2ipic_r_req_o (csr2ipic_r_req ),
|
| 514 |
|
|
.csr2ipic_w_req_o (csr2ipic_w_req ),
|
| 515 |
|
|
.csr2ipic_addr_o (csr2ipic_addr ),
|
| 516 |
|
|
.csr2ipic_wdata_o (csr2ipic_wdata ),
|
| 517 |
|
|
.ipic2csr_rdata_i (ipic2csr_rdata ),
|
| 518 |
|
|
`endif // SCR1_IPIC_EN
|
| 519 |
|
|
|
| 520 |
|
|
// CSR <-> PC interface
|
| 521 |
|
|
.exu2csr_pc_curr_i (curr_pc ),
|
| 522 |
|
|
.exu2csr_pc_next_i (next_pc ),
|
| 523 |
|
|
`ifndef SCR1_CSR_REDUCED_CNT
|
| 524 |
|
|
.exu2csr_instret_no_exc_i (instret_nexc ),
|
| 525 |
|
|
`endif // SCR1_CSR_REDUCED_CNT
|
| 526 |
|
|
|
| 527 |
|
|
// IRQ
|
| 528 |
|
|
`ifdef SCR1_IPIC_EN
|
| 529 |
|
|
.soc2csr_irq_ext_i (ipic2csr_irq ),
|
| 530 |
|
|
`else // SCR1_IPIC_EN
|
| 531 |
|
|
.soc2csr_irq_ext_i (soc2pipe_irq_ext_i ),
|
| 532 |
|
|
`endif // SCR1_IPIC_EN
|
| 533 |
|
|
.soc2csr_irq_soft_i (soc2pipe_irq_soft_i ),
|
| 534 |
|
|
.soc2csr_irq_mtimer_i (soc2pipe_irq_mtimer_i ),
|
| 535 |
|
|
|
| 536 |
|
|
// Memory-mapped external timer
|
| 537 |
|
|
.soc2csr_mtimer_val_i (soc2pipe_mtimer_val_i ),
|
| 538 |
|
|
|
| 539 |
|
|
`ifdef SCR1_DBG_EN
|
| 540 |
|
|
// CSR <-> HDU interface
|
| 541 |
|
|
.csr2hdu_req_o (csr2hdu_req ),
|
| 542 |
|
|
.csr2hdu_cmd_o (csr2hdu_cmd ),
|
| 543 |
|
|
.csr2hdu_addr_o (csr2hdu_addr ),
|
| 544 |
|
|
.csr2hdu_wdata_o (csr2hdu_wdata ),
|
| 545 |
|
|
.hdu2csr_rdata_i (hdu2csr_rdata ),
|
| 546 |
|
|
.hdu2csr_resp_i (hdu2csr_resp ),
|
| 547 |
|
|
.hdu2csr_no_commit_i (exu_no_commit ),
|
| 548 |
|
|
`endif // SCR1_DBG_EN
|
| 549 |
|
|
|
| 550 |
|
|
`ifdef SCR1_TDU_EN
|
| 551 |
|
|
// CSR <-> TDU interface
|
| 552 |
|
|
.csr2tdu_req_o (csr2tdu_req ),
|
| 553 |
|
|
.csr2tdu_cmd_o (csr2tdu_cmd ),
|
| 554 |
|
|
.csr2tdu_addr_o (csr2tdu_addr ),
|
| 555 |
|
|
.csr2tdu_wdata_o (csr2tdu_wdata ),
|
| 556 |
|
|
.tdu2csr_rdata_i (tdu2csr_rdata ),
|
| 557 |
|
|
.tdu2csr_resp_i (tdu2csr_resp ),
|
| 558 |
|
|
`endif // SCR1_TDU_EN
|
| 559 |
|
|
.soc2csr_fuse_mhartid_i (soc2pipe_fuse_mhartid_i )
|
| 560 |
|
|
);
|
| 561 |
|
|
|
| 562 |
|
|
//-------------------------------------------------------------------------------
|
| 563 |
|
|
// Integrated programmable interrupt controller
|
| 564 |
|
|
//-------------------------------------------------------------------------------
|
| 565 |
|
|
`ifdef SCR1_IPIC_EN
|
| 566 |
|
|
scr1_ipic i_pipe_ipic (
|
| 567 |
|
|
.rst_n (pipe_rst_n ),
|
| 568 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 569 |
|
|
.clk (clkctl2pipe_clk_alw_on_i),
|
| 570 |
|
|
`else // SCR1_CLKCTRL_EN
|
| 571 |
|
|
.clk (clk ),
|
| 572 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 573 |
|
|
.soc2ipic_irq_lines_i (soc2pipe_irq_lines_i ),
|
| 574 |
|
|
.csr2ipic_r_req_i (csr2ipic_r_req ),
|
| 575 |
|
|
.csr2ipic_w_req_i (csr2ipic_w_req ),
|
| 576 |
|
|
.csr2ipic_addr_i (csr2ipic_addr ),
|
| 577 |
|
|
.csr2ipic_wdata_i (csr2ipic_wdata ),
|
| 578 |
|
|
.ipic2csr_rdata_o (ipic2csr_rdata ),
|
| 579 |
|
|
.ipic2csr_irq_m_req_o (ipic2csr_irq )
|
| 580 |
|
|
);
|
| 581 |
|
|
`endif // SCR1_IPIC_EN
|
| 582 |
|
|
|
| 583 |
|
|
//-------------------------------------------------------------------------------
|
| 584 |
|
|
// Breakpoint module
|
| 585 |
|
|
//-------------------------------------------------------------------------------
|
| 586 |
|
|
`ifdef SCR1_TDU_EN
|
| 587 |
|
|
scr1_pipe_tdu i_pipe_tdu (
|
| 588 |
|
|
// Common signals
|
| 589 |
|
|
`ifdef SCR1_DBG_EN
|
| 590 |
|
|
.rst_n (dbg_rst_n ),
|
| 591 |
|
|
`else
|
| 592 |
|
|
.rst_n (rst_n ),
|
| 593 |
|
|
`endif // SCR1_DBG_EN
|
| 594 |
|
|
.clk (clk ),
|
| 595 |
|
|
.clk_en (1'b1 ),
|
| 596 |
|
|
`ifdef SCR1_DBG_EN
|
| 597 |
|
|
.tdu_dsbl_i (hwbrk_dsbl ),
|
| 598 |
|
|
`else // SCR1_DBG_EN
|
| 599 |
|
|
.tdu_dsbl_i (1'b0 ),
|
| 600 |
|
|
`endif // SCR1_DBG_EN
|
| 601 |
|
|
|
| 602 |
|
|
// TDU <-> CSR interface
|
| 603 |
|
|
`ifdef SCR1_DBG_EN
|
| 604 |
|
|
.csr2tdu_req_i (csr2tdu_req_qlfy ),
|
| 605 |
|
|
.csr2tdu_cmd_i (csr2tdu_cmd ),
|
| 606 |
|
|
.csr2tdu_addr_i (csr2tdu_addr ),
|
| 607 |
|
|
.csr2tdu_wdata_i (csr2tdu_wdata ),
|
| 608 |
|
|
`else // SCR1_DBG_EN
|
| 609 |
|
|
.csr2tdu_req_i (csr2tdu_req ),
|
| 610 |
|
|
.csr2tdu_cmd_i (csr2tdu_cmd ),
|
| 611 |
|
|
.csr2tdu_addr_i (csr2tdu_addr ),
|
| 612 |
|
|
.csr2tdu_wdata_i (csr2tdu_wdata ),
|
| 613 |
|
|
`endif // SCR1_DBG_EN
|
| 614 |
|
|
.tdu2csr_rdata_o (tdu2csr_rdata ),
|
| 615 |
|
|
.tdu2csr_resp_o (tdu2csr_resp ),
|
| 616 |
|
|
|
| 617 |
|
|
// TDU <-> EXU interface
|
| 618 |
|
|
`ifdef SCR1_DBG_EN
|
| 619 |
|
|
.exu2tdu_imon_i (exu2tdu_i_mon_qlfy ),
|
| 620 |
|
|
`else // SCR1_DBG_EN
|
| 621 |
|
|
.exu2tdu_imon_i (exu2tdu_i_mon ),
|
| 622 |
|
|
`endif // SCR1_DBG_EN
|
| 623 |
|
|
.tdu2exu_ibrkpt_match_o (tdu2exu_i_match ),
|
| 624 |
|
|
.tdu2exu_ibrkpt_exc_req_o (tdu2exu_i_x_req ),
|
| 625 |
|
|
`ifdef SCR1_DBG_EN
|
| 626 |
|
|
.exu2tdu_bp_retire_i (exu2tdu_bp_retire_qlfy),
|
| 627 |
|
|
`else // SCR1_DBG_EN
|
| 628 |
|
|
.exu2tdu_bp_retire_i (exu2tdu_bp_retire ),
|
| 629 |
|
|
`endif // SCR1_DBG_EN
|
| 630 |
|
|
|
| 631 |
|
|
// TDU <-> LSU interface
|
| 632 |
|
|
.tdu2lsu_ibrkpt_exc_req_o (tdu2lsu_i_x_req ),
|
| 633 |
|
|
`ifdef SCR1_DBG_EN
|
| 634 |
|
|
.lsu2tdu_dmon_i (lsu2tdu_d_mon_qlfy ),
|
| 635 |
|
|
`else // SCR1_DBG_EN
|
| 636 |
|
|
.lsu2tdu_dmon_i (lsu2tdu_d_mon ),
|
| 637 |
|
|
`endif // SCR1_DBG_EN
|
| 638 |
|
|
.tdu2lsu_dbrkpt_match_o (tdu2lsu_d_match ),
|
| 639 |
|
|
.tdu2lsu_dbrkpt_exc_req_o (tdu2lsu_d_x_req ),
|
| 640 |
|
|
// EPU I/F
|
| 641 |
|
|
`ifdef SCR1_DBG_EN
|
| 642 |
|
|
.tdu2hdu_dmode_req_o (tdu2hdu_dmode_req )
|
| 643 |
|
|
`else // SCR1_DBG_EN
|
| 644 |
|
|
.tdu2hdu_dmode_req_o ( )
|
| 645 |
|
|
`endif // SCR1_DBG_EN
|
| 646 |
|
|
);
|
| 647 |
|
|
|
| 648 |
|
|
`ifdef SCR1_DBG_EN
|
| 649 |
|
|
assign hwbrk_dsbl = (~dbg_en) | hdu_hwbrk_dsbl;
|
| 650 |
|
|
//
|
| 651 |
|
|
assign csr2tdu_req_qlfy = dbg_en & csr2tdu_req & pipe2hdu_rdc_qlfy_i;
|
| 652 |
|
|
//
|
| 653 |
|
|
assign exu2tdu_i_mon_qlfy.vd = exu2tdu_i_mon.vd & pipe2hdu_rdc_qlfy_i;
|
| 654 |
|
|
assign exu2tdu_i_mon_qlfy.req = exu2tdu_i_mon.req;
|
| 655 |
|
|
assign exu2tdu_i_mon_qlfy.addr = exu2tdu_i_mon.addr;
|
| 656 |
|
|
assign lsu2tdu_d_mon_qlfy.vd = lsu2tdu_d_mon.vd & pipe2hdu_rdc_qlfy_i;
|
| 657 |
|
|
assign lsu2tdu_d_mon_qlfy.load = lsu2tdu_d_mon.load;
|
| 658 |
|
|
assign lsu2tdu_d_mon_qlfy.store = lsu2tdu_d_mon.store;
|
| 659 |
|
|
assign lsu2tdu_d_mon_qlfy.addr = lsu2tdu_d_mon.addr;
|
| 660 |
|
|
assign exu2tdu_bp_retire_qlfy = exu2tdu_bp_retire & {$bits(exu2tdu_bp_retire){pipe2hdu_rdc_qlfy_i}};
|
| 661 |
|
|
`endif // SCR1_DBG_EN
|
| 662 |
|
|
|
| 663 |
|
|
`endif // SCR1_TDU_EN
|
| 664 |
|
|
|
| 665 |
|
|
//-------------------------------------------------------------------------------
|
| 666 |
|
|
// HART Debug Unit (HDU)
|
| 667 |
|
|
//-------------------------------------------------------------------------------
|
| 668 |
|
|
`ifdef SCR1_DBG_EN
|
| 669 |
|
|
scr1_pipe_hdu i_pipe_hdu (
|
| 670 |
|
|
// Common signals
|
| 671 |
|
|
.rst_n (dbg_rst_n ),
|
| 672 |
|
|
.clk_en (dm2pipe_active_i ),
|
| 673 |
|
|
`ifdef SCR1_CLKCTRL_EN
|
| 674 |
|
|
.clk_pipe_en (clkctl2pipe_clk_en_i ),
|
| 675 |
|
|
.clk (clkctl2pipe_clk_dbgc_i),
|
| 676 |
|
|
`else
|
| 677 |
|
|
.clk (clk ),
|
| 678 |
|
|
`endif // SCR1_CLKCTRL_EN
|
| 679 |
|
|
|
| 680 |
|
|
// Control/status registers i/f
|
| 681 |
|
|
.csr2hdu_req_i (csr2hdu_req_qlfy ),
|
| 682 |
|
|
.csr2hdu_cmd_i (csr2hdu_cmd ),
|
| 683 |
|
|
.csr2hdu_addr_i (csr2hdu_addr ),
|
| 684 |
|
|
.csr2hdu_wdata_i (csr2hdu_wdata ),
|
| 685 |
|
|
.hdu2csr_resp_o (hdu2csr_resp ),
|
| 686 |
|
|
.hdu2csr_rdata_o (hdu2csr_rdata ),
|
| 687 |
|
|
|
| 688 |
|
|
// HART Run Control i/f
|
| 689 |
|
|
.pipe2hdu_rdc_qlfy_i (pipe2hdu_rdc_qlfy_i ),
|
| 690 |
|
|
.dm2hdu_cmd_req_i (dm2pipe_cmd_req_i ),
|
| 691 |
|
|
.dm2hdu_cmd_i (dm2pipe_cmd_i ),
|
| 692 |
|
|
.hdu2dm_cmd_resp_o (pipe2dm_cmd_resp_o ),
|
| 693 |
|
|
.hdu2dm_cmd_rcode_o (pipe2dm_cmd_rcode_o ),
|
| 694 |
|
|
.hdu2dm_hart_event_o (pipe2dm_hart_event_o ),
|
| 695 |
|
|
.hdu2dm_hart_status_o (pipe2dm_hart_status_o ),
|
| 696 |
|
|
|
| 697 |
|
|
// Program Buffer - HART instruction execution i/f
|
| 698 |
|
|
.hdu2dm_pbuf_addr_o (pipe2dm_pbuf_addr_o ),
|
| 699 |
|
|
.dm2hdu_pbuf_instr_i (dm2pipe_pbuf_instr_i ),
|
| 700 |
|
|
|
| 701 |
|
|
// HART Abstract Data regs i/f
|
| 702 |
|
|
.hdu2dm_dreg_req_o (pipe2dm_dreg_req_o ),
|
| 703 |
|
|
.hdu2dm_dreg_wr_o (pipe2dm_dreg_wr_o ),
|
| 704 |
|
|
.hdu2dm_dreg_wdata_o (pipe2dm_dreg_wdata_o ),
|
| 705 |
|
|
.dm2hdu_dreg_resp_i (dm2pipe_dreg_resp_i ),
|
| 706 |
|
|
.dm2hdu_dreg_fail_i (dm2pipe_dreg_fail_i ),
|
| 707 |
|
|
.dm2hdu_dreg_rdata_i (dm2pipe_dreg_rdata_i ),
|
| 708 |
|
|
//
|
| 709 |
|
|
`ifdef SCR1_TDU_EN
|
| 710 |
|
|
// HDU <-> TDU interface
|
| 711 |
|
|
.hdu2tdu_hwbrk_dsbl_o (hdu_hwbrk_dsbl ),
|
| 712 |
|
|
.tdu2hdu_dmode_req_i (tdu2hdu_dmode_req ),
|
| 713 |
|
|
.exu2hdu_ibrkpt_hw_i (brkpt_hw ),
|
| 714 |
|
|
`endif // SCR1_TDU_EN
|
| 715 |
|
|
|
| 716 |
|
|
// HART Run Status
|
| 717 |
|
|
.pipe2hdu_exu_busy_i (exu_busy_qlfy ),
|
| 718 |
|
|
.pipe2hdu_instret_i (instret_qlfy ),
|
| 719 |
|
|
.pipe2hdu_init_pc_i (exu_init_pc_qlfy ),
|
| 720 |
|
|
|
| 721 |
|
|
// HART Halt Status
|
| 722 |
|
|
.pipe2hdu_exu_exc_req_i (exu_exc_req_qlfy ),
|
| 723 |
|
|
.pipe2hdu_brkpt_i (brkpt_qlfy ),
|
| 724 |
|
|
|
| 725 |
|
|
// HART Run Control
|
| 726 |
|
|
.hdu2exu_pbuf_fetch_o (fetch_pbuf ),
|
| 727 |
|
|
.hdu2exu_no_commit_o (exu_no_commit ),
|
| 728 |
|
|
.hdu2exu_irq_dsbl_o (exu_irq_dsbl ),
|
| 729 |
|
|
.hdu2exu_pc_advmt_dsbl_o (exu_pc_advmt_dsbl ),
|
| 730 |
|
|
.hdu2exu_dmode_sstep_en_o (exu_dmode_sstep_en ),
|
| 731 |
|
|
|
| 732 |
|
|
// HART state
|
| 733 |
|
|
.hdu2exu_dbg_halted_o (dbg_halted ),
|
| 734 |
|
|
.hdu2exu_dbg_run2halt_o (dbg_run2halt ),
|
| 735 |
|
|
.hdu2exu_dbg_halt2run_o (dbg_halt2run ),
|
| 736 |
|
|
.hdu2exu_dbg_run_start_o (dbg_run_start ),
|
| 737 |
|
|
|
| 738 |
|
|
// PC interface
|
| 739 |
|
|
.pipe2hdu_pc_curr_i (curr_pc ),
|
| 740 |
|
|
.hdu2exu_dbg_new_pc_o (dbg_new_pc ),
|
| 741 |
|
|
|
| 742 |
|
|
// Prgram Buffer Instruction interface
|
| 743 |
|
|
.ifu2hdu_pbuf_instr_rdy_i (ifu2hdu_pbuf_rdy_qlfy ),
|
| 744 |
|
|
.hdu2ifu_pbuf_instr_vd_o (hdu2ifu_pbuf_vd ),
|
| 745 |
|
|
.hdu2ifu_pbuf_instr_err_o (hdu2ifu_pbuf_err ),
|
| 746 |
|
|
.hdu2ifu_pbuf_instr_o (hdu2ifu_pbuf_instr )
|
| 747 |
|
|
);
|
| 748 |
|
|
|
| 749 |
|
|
assign csr2hdu_req_qlfy = csr2hdu_req & dbg_en & pipe2hdu_rdc_qlfy_i;
|
| 750 |
|
|
//
|
| 751 |
|
|
assign exu_busy_qlfy = exu_busy & {$bits(exu_busy){pipe2hdu_rdc_qlfy_i}};
|
| 752 |
|
|
assign instret_qlfy = instret & {$bits(instret){pipe2hdu_rdc_qlfy_i}};
|
| 753 |
|
|
assign exu_init_pc_qlfy = exu_init_pc & {$bits(exu_init_pc){pipe2hdu_rdc_qlfy_i}};
|
| 754 |
|
|
assign exu_exc_req_qlfy = exu_exc_req & {$bits(exu_exc_req){pipe2hdu_rdc_qlfy_i}};
|
| 755 |
|
|
assign brkpt_qlfy = brkpt & {$bits(brkpt){pipe2hdu_rdc_qlfy_i}};
|
| 756 |
|
|
assign ifu2hdu_pbuf_rdy_qlfy = ifu2hdu_pbuf_rdy & {$bits(ifu2hdu_pbuf_rdy){pipe2hdu_rdc_qlfy_i}};
|
| 757 |
|
|
|
| 758 |
|
|
`endif // SCR1_DBG_EN
|
| 759 |
|
|
|
| 760 |
|
|
`ifdef SCR1_TRGT_SIMULATION
|
| 761 |
|
|
//-------------------------------------------------------------------------------
|
| 762 |
|
|
// Tracelog
|
| 763 |
|
|
//-------------------------------------------------------------------------------
|
| 764 |
|
|
|
| 765 |
|
|
scr1_tracelog i_tracelog (
|
| 766 |
|
|
.rst_n (pipe_rst_n ),
|
| 767 |
|
|
.clk (clk ),
|
| 768 |
|
|
.soc2pipe_fuse_mhartid_i (soc2pipe_fuse_mhartid_i ),
|
| 769 |
|
|
|
| 770 |
|
|
// MPRF
|
| 771 |
|
|
.mprf2trace_int_i (i_pipe_mprf.mprf_int ),
|
| 772 |
|
|
.mprf2trace_wr_en_i (i_pipe_mprf.exu2mprf_w_req_i ),
|
| 773 |
|
|
.mprf2trace_wr_addr_i (i_pipe_mprf.exu2mprf_rd_addr_i ),
|
| 774 |
|
|
.mprf2trace_wr_data_i (i_pipe_mprf.exu2mprf_rd_data_i ),
|
| 775 |
|
|
|
| 776 |
|
|
// EXU
|
| 777 |
|
|
.exu2trace_update_pc_en_i (i_pipe_exu.update_pc_en ),
|
| 778 |
|
|
.exu2trace_update_pc_i (i_pipe_exu.update_pc ),
|
| 779 |
|
|
|
| 780 |
|
|
// IFU
|
| 781 |
|
|
.ifu2trace_instr_i (i_pipe_ifu.ifu2idu_instr_o ),
|
| 782 |
|
|
|
| 783 |
|
|
// CSR
|
| 784 |
|
|
.csr2trace_mstatus_mie_i (i_pipe_csr.csr_mstatus_mie_ff ),
|
| 785 |
|
|
.csr2trace_mstatus_mpie_i (i_pipe_csr.csr_mstatus_mpie_ff ),
|
| 786 |
|
|
.csr2trace_mtvec_base_i (i_pipe_csr.csr_mtvec_base ),
|
| 787 |
|
|
.csr2trace_mtvec_mode_i (i_pipe_csr.csr_mtvec_mode ),
|
| 788 |
|
|
.csr2trace_mie_meie_i (i_pipe_csr.csr_mie_meie_ff ),
|
| 789 |
|
|
.csr2trace_mie_mtie_i (i_pipe_csr.csr_mie_mtie_ff ),
|
| 790 |
|
|
.csr2trace_mie_msie_i (i_pipe_csr.csr_mie_msie_ff ),
|
| 791 |
|
|
.csr2trace_mip_meip_i (i_pipe_csr.csr_mip_meip ),
|
| 792 |
|
|
.csr2trace_mip_mtip_i (i_pipe_csr.csr_mip_mtip ),
|
| 793 |
|
|
.csr2trace_mip_msip_i (i_pipe_csr.csr_mip_msip ),
|
| 794 |
|
|
.csr2trace_mepc_i (i_pipe_csr.csr_mepc_ff ),
|
| 795 |
|
|
.csr2trace_mcause_irq_i (i_pipe_csr.csr_mcause_i_ff ),
|
| 796 |
|
|
.csr2trace_mcause_ec_i (i_pipe_csr.csr_mcause_ec_ff ),
|
| 797 |
|
|
.csr2trace_mtval_i (i_pipe_csr.csr_mtval_ff ),
|
| 798 |
|
|
.csr2trace_mstatus_mie_up_i (i_pipe_csr.csr2exu_mstatus_mie_up_o),
|
| 799 |
|
|
|
| 800 |
|
|
// Events
|
| 801 |
|
|
.csr2trace_e_exc_i (i_pipe_csr.e_exc ),
|
| 802 |
|
|
.csr2trace_e_irq_i (i_pipe_csr.e_irq ),
|
| 803 |
|
|
.pipe2trace_e_wake_i (pipe2clkctl_wake_req_o ),
|
| 804 |
|
|
.csr2trace_e_mret_i (i_pipe_csr.e_mret )
|
| 805 |
|
|
);
|
| 806 |
|
|
|
| 807 |
|
|
`endif // SCR1_TRGT_SIMULATION
|
| 808 |
|
|
|
| 809 |
|
|
endmodule : scr1_pipe_top
|
